Agilent Measurement Journal - Issue 5 - 2008 - (Page 22)

containing the downlink and uplink pilot timeslots (DwPTS and UpPTS) separated by a transmission gap (GP). The allocation of the subframes for the uplink, downlink and special subframes is determined by one of seven different conﬁgurations. Subframes 0 and 5 are always downlink transmissions, while subframe 1 is always a special subframe. The composition of the other subframes varies depending on the conﬁguration. For a 5 ms switch-point conﬁguration, subframe 6 is always a special subframe as shown in Figure 6. With 10 ms switch-point periodicity, there is only one special subframe per 10-ms frame. The remainder of the article will focus on FS1 for the FDD downlink. Figure 7 shows the downlink resource grid for a 0.5-ms timeslot which incorporates the concepts of a resource element and a resource block. A resource element is the smallest identiﬁable unit of transmission and consists of one subcarrier for one symbol period. However, transmissions are scheduled in larger units called resource blocks which comprise 12 adjacent subcarriers for a period of one 0.5-ms timeslot. One radio frame, Tf = 307200 Ts = 10 ms One slot, Tslot = 15360 Ts = 0.5 ms #0 #1 #2 #3 #18 #19 Mapping the downlink Figure 8 presents a more detailed view of FS1 for the downlink, showing the downlink slot structure color coded for the different signals and channels. As the diagram shows, an entire 10-ms frame is required for the control channels to repeat. The frame structure is deﬁned in units of Ts, which is the shortest time interval of the system deﬁned as 1/(15000 x 2048) seconds or 32.552 ns. Figure 8 shows how the timeslot is divided up into seven symbols. Each symbol is extended by the length of the CP by copying the end of the symbol to the beginning. This process does not add new information to the signal. Rather, the CP adds redundancy to counteract the inter-symbol interference caused by multipath delay spread. Using the normal CP length of 144 x Ts (4.69 µs), it is necessary to make the ﬁrst CP slightly longer at 160 x Ts so that the timeslot adds up to 0.5 ms. The CP is chosen to be slightly longer than the longest expected delay spread in the radio channel. For LTE, the normal CP length enables the system to cope with path delay variations up to about 1.4 km. Note that this ﬁgure represents the difference in path length due to reﬂections, not the size of the cell. The mapping of the downlink physical signals and channels for the example in Figure 8 is as follows: carrier and symbol 4 of the fourth subcarrier of each slot. This is the simplest case for single-antenna use. The position of the RS varies with the antenna port number and the CP length. • P-SCH is transmitted on symbol 6 of slots 0 and 10 of each radio frame, and occupies 62 subcarriers centered on the DC subcarrier. • S-SCH is transmitted on symbol 5 of slots 0 and 10 of each radio frame, and occupies 62 subcarriers centered on the DC subcarrier. • PBCH is transmitted on symbol 0 to 3 of slot 1 of each radio frame, and occupies 72 subcarriers centered on the DC subcarrier. For simplicity, the PMCH, PCFICH and PHICH are not shown in this example. Note that the control channels are contained within the central 1.08 MHz of the signal so that system operation can be independent of the channel bandwidth. The length One sub-frame One downlink slot, Tslot NDL OFDM symbols symb k = NDL x NRB – 1 RB sc NDL x NRB subcarriers RB sc NRB subcarriers sc Resource block RB NDL x Nsc resource elements symb Resource element (k, l) l=0 k=0 l = NDL – 1 symb Figure 7. Downlink resource grid (TS 36.211. V8.2.0 Figure 6.2.2-1) 22 Agilent Measurement Journal

Table of Contents Feed for the Digital Edition of Agilent Measurement Journal - Issue 5 - 2008

Agilent Measurement Journal Issue 5 Finding a New Path when Assumptions Break Down Contents Testing MIPI D-PHY Protocols Oscilloscope Firmware Update DNA Replication Joining the LTE/SAE Trial Initiative Testing Proteins Praise for DC Power Analyzer Scripting Features for AMDS Testing Hybrid PCBA Systems Improving the Gene Expression System Workflow Turning a “Good Enough” Test Strategy into One That’s Reliable, Repeatable and Traceable Understanding the Effects of Limited-Bandwidth Channels on Digital Data Signals Introducing the 3GPP LTE Downlink Validating the 26 Validating the Physical and Protocol Layers in DDR Memory Interfaces Understanding Total Jitter Measurements of Low Probabilities Using Behavioral-Model Simulation to Accurately Predict First-Order PLL Performance Creating Synchronous High-Frequency Sampling across Multiple Digitizers Overcoming the Challenges of Testing FlexRay Networks Understanding Operating Life and Repeatability of Electromechanical Switches and their Effect on Total Cost of Ownership Implementing Micro and Nano LC/MS Techniques for High Sensitivity Lipidomics Analysis

Agilent Measurement Journal - Issue 5 - 2008

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