Agilent Measurement Journal - Issue 5 - 2008 - (Page 27)

M Memory devices are found almost everywhere, from computers and phones to HDTV sets and automobiles. One of today’s most commonly used technologies is double data rate (DDR) synchronous dynamic random access memory (SDRAM). DDR technology is now in its third generation (DDR3) and offers faster transfer rates and lower energy consumption than previous versions. The internal DDR architecture is special because it relies on parallel, single-ended signals that operate at the speed of today’s new serial technologies. From a purely electrical perspective, parallel and serial buses generally don’t work well together due to the interference generated between adjacent bus lines. Also, most of today’s common high-speed architectures consist of differential signals that inherently reject common-mode noise. Thus, problems such as crosstalk, impedance mismatch, electromagnetic interference (EMI), jitter, and noise become highly likely in and around DDR devices. When characterizing DDR devices, probe loading also can affect the performance of measured signals. As transfer rates increase, performance within the physical and protocol layers becomes increasingly important due to reductions in signal amplitude and timing margin — and performance in those layers is the key to system interoperability. Failures in the physical layer are correlated with protocol failures such as marginal timing relationships, protocol violations, clock jitter issues, and errors from other buses. After physical-layer validation has been performed, timing relationships and protocol violations can then be veriﬁed. After outlining the challenges in validating DDR at the physical and protocol layers, this article suggests a few viable measurement methods that can overcome those challenges. These techniques are applicable to all DDR technologies and to the DDR side of fully buffered dual inline memory modules (FB-DIMMs). Overview: Probing methods The Joint Electronic Device Engineering Council (JEDEC) speciﬁes the DDR physical layer speciﬁcations in DDR devices for both the memory controller and the DDR DRAM. For true physical-layer compliance with the speciﬁcation, the recommended approach is to probe at the DDR DRAM ball-grid-array (BGA) package ballout. This will provide greater insight into signal performance when performing physical layer testing. Because all signals are hidden beneath the package, however, it is difﬁcult to probe directly at the DDR BGA ballout. The next best probing location is at the signal vias on the back of the circuit board because these are closest to the DRAM ballout. Unfortunately, signal vias may not be present if components are densely arrayed on both sides of a circuit board. This suggests probing elsewhere, perhaps at signal traces or surface-mount resistors and capacitors. Although this might seem straightforward and easy, it often compromises the measurement Agilent Measurement Journal 27

Table of Contents Feed for the Digital Edition of Agilent Measurement Journal - Issue 5 - 2008

Agilent Measurement Journal Issue 5 Finding a New Path when Assumptions Break Down Contents Testing MIPI D-PHY Protocols Oscilloscope Firmware Update DNA Replication Joining the LTE/SAE Trial Initiative Testing Proteins Praise for DC Power Analyzer Scripting Features for AMDS Testing Hybrid PCBA Systems Improving the Gene Expression System Workflow Turning a “Good Enough” Test Strategy into One That’s Reliable, Repeatable and Traceable Understanding the Effects of Limited-Bandwidth Channels on Digital Data Signals Introducing the 3GPP LTE Downlink Validating the 26 Validating the Physical and Protocol Layers in DDR Memory Interfaces Understanding Total Jitter Measurements of Low Probabilities Using Behavioral-Model Simulation to Accurately Predict First-Order PLL Performance Creating Synchronous High-Frequency Sampling across Multiple Digitizers Overcoming the Challenges of Testing FlexRay Networks Understanding Operating Life and Repeatability of Electromechanical Switches and their Effect on Total Cost of Ownership Implementing Micro and Nano LC/MS Techniques for High Sensitivity Lipidomics Analysis

Agilent Measurement Journal - Issue 5 - 2008

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