Agilent Measurement Journal - Issue 5 - 2008 - (Page 29)

If the traces on the BGA probe adapter are designed with the same length, there is no skew between the signals. Inside the adapter, embedded resistors placed near the DDR signals prevent probe loading from interfering with the DDR signals. This design minimizes the capacitive loading of the stubs and probe, preserving operation of the high-speed DDR interface without impacting the actual signals. Waveforms obtained this way more closely represent actual signal performance and thereby provide highly accurate results for physical- and protocol-layer validation. Amplitude triggering: In some cases, it is possible to isolate the read and write signals if one is larger than the other; however, the read and write signals sometimes have similar amplitudes. As a result, predicting when this will be an effective way to separate the waveforms can be difﬁcult. Command-signal triggering: An MSO includes both analog and digital (logic) channels and can measure them simultaneously. As the DDR command signals are asserted during different operations, they can be used to trigger measurements of strobe and data signals. This is done by connecting the command signals to the MSO logic channels and the strobe and data signals to the MSO analog channels. There is one caveat: The bandwidth of a typical MSO is best suited to DDR devices with transfer rates of less than 400 MT/s. Examining the challenges in physical-layer validation During physical validation, bi-directional transmission of strobe and data signals on the bus makes it difﬁcult to separate the trafﬁc moving between the memory controller and the DDR device. Examining these signals separately is required to enable independent analysis of their electrical and timing characteristics. If the signals cannot be isolated, it will be impossible to characterize the performance of the memory controller and the DDR device. Three methods may be used to separate the read and write waveforms: triggering on the preamble bit width, triggering on the amplitude of the read or write signal and triggering on the command signals using a mixed-signal oscilloscope (MSO). Unfortunately, each of these separation methods has important limitations. Width triggering: Because the JEDEC deﬁnition of the write preamble width is somewhat vague, it is best to assume a large variation in the width. In most cases, however, the write preamble width is similar to that of either the read preamble or the regular data-bit period. Due to these issues, there is a high likelihood that this separation method will not be effective. Addressing the challenges The latest oscilloscopes offer new capabilities that overcome the challenges of separating read and write signals, and also reduce the time and effort required to fully characterize a design. Examples include zone triggering and automated compliance measurements. With these functions, it is possible to exhaustively characterize and validate a memory interface in much less time than is required with manual methods. Read and write separation with zone triggering Setting the scope display to inﬁnite persistence makes it possible to observe distinctive differences between read and write signal patterns. This is possible for two reasons: The data signals have different phase relative to the strobe signals, and no two pieces of silicon have identical electrical characteristics. By observing and understanding the meaning of these distinctive differences, it is possible to identify and isolate “zones” associated with the patterns of read and write signals. In Figure 2, the DDR signal shows distinctive patterns that can be isolated with a zone-triggering function. Once the read and write signals are separated, each can be easily measured. Agilent Measurement Journal 29

Table of Contents Feed for the Digital Edition of Agilent Measurement Journal - Issue 5 - 2008

Agilent Measurement Journal Issue 5 Finding a New Path when Assumptions Break Down Contents Testing MIPI D-PHY Protocols Oscilloscope Firmware Update DNA Replication Joining the LTE/SAE Trial Initiative Testing Proteins Praise for DC Power Analyzer Scripting Features for AMDS Testing Hybrid PCBA Systems Improving the Gene Expression System Workflow Turning a “Good Enough” Test Strategy into One That’s Reliable, Repeatable and Traceable Understanding the Effects of Limited-Bandwidth Channels on Digital Data Signals Introducing the 3GPP LTE Downlink Validating the 26 Validating the Physical and Protocol Layers in DDR Memory Interfaces Understanding Total Jitter Measurements of Low Probabilities Using Behavioral-Model Simulation to Accurately Predict First-Order PLL Performance Creating Synchronous High-Frequency Sampling across Multiple Digitizers Overcoming the Challenges of Testing FlexRay Networks Understanding Operating Life and Repeatability of Electromechanical Switches and their Effect on Total Cost of Ownership Implementing Micro and Nano LC/MS Techniques for High Sensitivity Lipidomics Analysis

Agilent Measurement Journal - Issue 5 - 2008

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