Agilent Measurement Journal - Issue 5 - 2008 - (Page 30)

Data strobe (DQS) read or write normal bits DQS read or write normal bits Idle state DQS read or write preamble bits Idle state The zone-trigger capability makes it possible to separate the read or write cycles. “Must not intersect” zone “Must intersect” zone Figure 2. The zone-trigger capability makes it possible to separate the read or write cycles. Automated measurements with a DDR application Separating the read and write signals is just the ﬁrst step of the validation task. It is still necessary to spend time with an oscilloscope manually validating each test parameter deﬁned in the JEDEC speciﬁcation. Because this is a very long list, however, it is often difﬁcult to exhaustively characterize every test parameter. Even more problematic, the results must be manually recorded and formatted in a test report. To save time and effort, many of the required steps can be automated with dedicated “applications” built into an oscilloscope. Using these automated routines, measurements of every test parameter can be repeated multiple times to thoroughly analyze a signal with complete statistical results, along with screen captures of worst-case results. Many applications also automatically generate comprehensive test reports for archiving or sharing. Overcoming challenges in protocol-layer validation As the DDR transfer rate gets faster, two common challenges crop up: signal-sampling position and signal correlation. Some logic analyzers provide capabilities that address these issues. Signal-sampling position adjustment The DDR technology transfer rate is quickly catching up with the sampling rate of the logic analyzer. As the data-valid window becomes smaller, a logic analyzer has to sample at the right position on the signal bit to capture the correct data. If the data is sampled outside of the data-valid window, the wrong data will be captured because the signal is sampled at a quasi-state or an invalid transition state. A “high” state may then be misinterpreted as a “low” state, or vice versa, and the logic analyzer may interpret the protocol incorrectly and consequently detect a too-high bit error rate. 30 Agilent Measurement Journal

Table of Contents Feed for the Digital Edition of Agilent Measurement Journal - Issue 5 - 2008

Agilent Measurement Journal Issue 5 Finding a New Path when Assumptions Break Down Contents Testing MIPI D-PHY Protocols Oscilloscope Firmware Update DNA Replication Joining the LTE/SAE Trial Initiative Testing Proteins Praise for DC Power Analyzer Scripting Features for AMDS Testing Hybrid PCBA Systems Improving the Gene Expression System Workflow Turning a “Good Enough” Test Strategy into One That’s Reliable, Repeatable and Traceable Understanding the Effects of Limited-Bandwidth Channels on Digital Data Signals Introducing the 3GPP LTE Downlink Validating the 26 Validating the Physical and Protocol Layers in DDR Memory Interfaces Understanding Total Jitter Measurements of Low Probabilities Using Behavioral-Model Simulation to Accurately Predict First-Order PLL Performance Creating Synchronous High-Frequency Sampling across Multiple Digitizers Overcoming the Challenges of Testing FlexRay Networks Understanding Operating Life and Repeatability of Electromechanical Switches and their Effect on Total Cost of Ownership Implementing Micro and Nano LC/MS Techniques for High Sensitivity Lipidomics Analysis

Agilent Measurement Journal - Issue 5 - 2008

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