Agilent Measurement Journal - Issue 5 - 2008 - (Page 31)

To avoid quasi-state errors, some logic analyzers provide high-resolution data sampling capabilities that allow accurate sampling positioning of read and write data (Figure 3). The eye diagram provides comprehensive signal integrity information on all of the memory buses. The sample position can be adjusted to the center of the eye opening with 10 ps horizontal and 10 mV vertical resolution, enabling precise acquisition of accurate read and write data. Signal correlation with protocol-aware sampling The DDR3 and DDR2 DIMM architectures are markedly different, with DDR3 using a ﬂ y-by topology and DDR2 using a T-branch topology. In DDR2, the T-branch balances the signal delays to each memory device; however, the topology makes it difﬁcult to manage signal reﬂections. In contrast, the ﬂ y-by topology used in DDR3 improves signal integrity on the command and address buses. The downside, however, is that signals from the memory controller arrive at each DDR DRAM at different times, causing skew. If no timing compensation is made, some signals will not be correlated. For example, if command or address samples are not correlated with the associated strobe and data information, protocol violations will occur. A logic analyzer equipped with protocol-aware sampling and a time-adjustable delay circuit can compensate for the skew. With this capability, read and write cycle signals are properly aligned with the center of the eye opening and all signals will be time correlated. This ensures proper association of command and address signals with strobe and data, as well as accurate protocol-layer validation. Conclusion Rapidly evolving DDR memory technology is driving the need for new design and validation methods. With DDR speeds climbing higher to match those of the latest high-speed serial technologies, it is more likely that probe loading will distort the signal waveforms. For that reason alone, it is essential to pay special attention to probing — and every signal integrity measurement begins at the probe tip and reaches all the way back into the oscilloscope and logic analyzer. The ability to access all memory signals is important for full functional debug and testing with the logic analyzer. New capabilities now being built into oscilloscopes and logic analyzers greatly simplify the physical and protocol validation of DDR devices and interfaces. Blue indicator points to the middle of the eye Adjustment of sample position as ﬁne as 10-ps/10-mV resolution Figure 3. In protocol measurements, adjusting the logic analyzer sampling position to the center of the eye opening will maximize sampling accuracy. Agilent Measurement Journal 31

Table of Contents Feed for the Digital Edition of Agilent Measurement Journal - Issue 5 - 2008

Agilent Measurement Journal Issue 5 Finding a New Path when Assumptions Break Down Contents Testing MIPI D-PHY Protocols Oscilloscope Firmware Update DNA Replication Joining the LTE/SAE Trial Initiative Testing Proteins Praise for DC Power Analyzer Scripting Features for AMDS Testing Hybrid PCBA Systems Improving the Gene Expression System Workflow Turning a “Good Enough” Test Strategy into One That’s Reliable, Repeatable and Traceable Understanding the Effects of Limited-Bandwidth Channels on Digital Data Signals Introducing the 3GPP LTE Downlink Validating the 26 Validating the Physical and Protocol Layers in DDR Memory Interfaces Understanding Total Jitter Measurements of Low Probabilities Using Behavioral-Model Simulation to Accurately Predict First-Order PLL Performance Creating Synchronous High-Frequency Sampling across Multiple Digitizers Overcoming the Challenges of Testing FlexRay Networks Understanding Operating Life and Repeatability of Electromechanical Switches and their Effect on Total Cost of Ownership Implementing Micro and Nano LC/MS Techniques for High Sensitivity Lipidomics Analysis

Agilent Measurement Journal - Issue 5 - 2008

For optimal viewing of this digital publication, please enable JavaScript and then refresh the page. If you would like to try to load the digital publication without using Flash Player detection, please click here.