Agilent Measurement Journal - Issue 5 - 2008 - (Page 45)

P Phase-locked loops (PLLs) are widely used as on-chip clock generators to synthesize and reshape a high-frequency internal signal that is derived from a lower-frequency external signal. In data communications, for example, PLLs are used as clock-recovery systems. In broadband optical communication networks, they serve as clock-and-data recovery (CDR) systems that generate the clock and resynchronize the data from the received signal. PLLs are also used as frequency synthesizers in wireless communications to synthesize an accurate frequency that can then be used to modulate or demodulate the incoming signals. The random temporal variation of phase in the synthesized frequency is an essential measure of PLL performance. This “phase noise” or “jitter” is an undesired variation in the timing of events at the output of the PLL — and it is difﬁcult to predict with the small-signal analysis capabilities of traditional circuit simulators. Because a PLL generates repetitive switching events as an essential part of its operation, the noise performance must be evaluated in the presence of this large-signal behavior. Some design tools are well-suited to the simulation and characterization of noise performance in small circuits such as voltage-controlled oscillators (VCOs). However, a closed-loop PLL synthesizer may have a device gate count of 30,000 to 50,000, making it hard for some simulators to converge on a result. In contrast, the Agilent RF Design Environment (RFDE) and Advanced Design System (ADS) tools feature the capability to characterize noise performance and create behavioral models for every subcircuit of a PLL synthesizer. The phase noise or jitter performance of each subcircuit can be simulated separately with RFDE while noise parameters can be extracted for behavior modeling. Using the Agilent EEsof circuit-envelope capability, a closed-loop simulation can then be performed in a matter of several seconds. Due to the nonlinear nature of oscillator circuits, amplitude ﬂuctuation is inherently limited and phase variation is of key importance. Variations in phase — both short-term nonrandom and long-term — are usually due to an external reference source and discrete spurious signals, which can be removed or suppressed to a reasonable level using appropriate techniques. Short-term random variation in phase, which is the phase noise or jitter mentioned earlier, directly impacts the accuracy and stability of PLL performance. If the ideal output signal of an oscillator is sinusoidal (e.g., phasor), then the noise is a small perturbation added to this trajectory as shown: Equation 1. S (t) [A 1 + n1 (t)]cos[w0t + q(t)] In the equation, A1 is the constant amplitude, n1(t) is the amplitude (AM) noise (negligible in a well-designed oscillator), w0 is the waveform center frequency, and q(t) the waveform phase perturbation. Modulation theory shows that phase noise can be represented as a sideband with symmetrically smaller amplitude on both sides of the carrier frequency. Intuitively, phase noise in the frequency domain can be viewed as the cycle-to-cycle jitter in the time domain which changes the instantaneous zero-crossing of an otherwise perfect sinusoidal signal. There are ﬁve signiﬁcant sources of phase noise within a PLL synthesizer: • VCO phase noise • Reference-oscillator phase noise • Thermal noise and device noise from components in the loop ﬁlter • Noise from the digital dividers and phase detector Understanding PLL noise Unlike a single tone in a frequency spectrum, the synthesized output frequency of a PLL is subject to all sorts of noise, occurring in both amplitude and phase. Common sources such as ﬂick (1/f), thermal and shot noise are associated with devices. Comprehensive noise models also include additional sources such as power/ground, substrate noise coupling, signal intermodulation, and sub-optimum biasing. • Noise injected by the supplies and bias circuits The ﬁrst three sources are well understood and can usually be accurately modeled using measured phase-noise data for the VCO and reference, and conventional noise models from circuit theory for the loop ﬁlter. In contrast, noise from digital devices, dividers and phase/frequency detectors is difﬁcult to model and constrains top-level simulation of all analog and digital functional blocks. Agilent Measurement Journal 45

Table of Contents Feed for the Digital Edition of Agilent Measurement Journal - Issue 5 - 2008

Agilent Measurement Journal Issue 5 Finding a New Path when Assumptions Break Down Contents Testing MIPI D-PHY Protocols Oscilloscope Firmware Update DNA Replication Joining the LTE/SAE Trial Initiative Testing Proteins Praise for DC Power Analyzer Scripting Features for AMDS Testing Hybrid PCBA Systems Improving the Gene Expression System Workflow Turning a “Good Enough” Test Strategy into One That’s Reliable, Repeatable and Traceable Understanding the Effects of Limited-Bandwidth Channels on Digital Data Signals Introducing the 3GPP LTE Downlink Validating the 26 Validating the Physical and Protocol Layers in DDR Memory Interfaces Understanding Total Jitter Measurements of Low Probabilities Using Behavioral-Model Simulation to Accurately Predict First-Order PLL Performance Creating Synchronous High-Frequency Sampling across Multiple Digitizers Overcoming the Challenges of Testing FlexRay Networks Understanding Operating Life and Repeatability of Electromechanical Switches and their Effect on Total Cost of Ownership Implementing Micro and Nano LC/MS Techniques for High Sensitivity Lipidomics Analysis

Agilent Measurement Journal - Issue 5 - 2008

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