Agilent Measurement Journal - Issue 5 - 2008 - (Page 49)

Cp = 300µA –65 dBc/Hz –86 dBc/Hz –132 dBc/Hz As shown in this article, simulated results based on a PLL behavior model were consistent with measured results from an IC (allowing for the circuitry differences between the modeled and measured PLL). This work supports the idea that actual PLL performance can be predicted at the ﬁrst-order by using a robust behavioral model simulation. Figure 7. The measured phase noise of the PLL frequency synthesizer Table 1 compares simulated and measured PLL closed-loop phase noise at key frequencies. Taking into account the circuitry differences between the simulated and measured PLL, the simulated results can be used as a good ﬁrst-order prediction of the real PLL on the IC. Table 1. Simulated versus measured PLL closed-loop phase noise at two key frequencies Acknowledgements The author wishes to thank Yi Fang and Wei Zhang, formerly of M/A-COM, for their contributions to this article. He would also like to acknowledge the assistance of Andy Howard from Agilent Technologies on RFDE/ADS simulations and the support of Carlos Cardenas from M/A-COM on simulation tools. In December 2007, an earlier version of this article was published in two parts on the Planet Analog website, www.planetanalog.com. References 1. Leeson, D.B. 1966. A Simple Model of Feedback Oscillator Noise Spectrum. Proc. IEEE, Volume 54: 329-330. 2. Razavi, B. 1996. A Study of Phase Noise in CMOS Oscillators. IEEE J Solid-State Circuits, Volume 31, March 1996: 331-343. 3. Hajimiri, A. and Lee, T.H. 1998. A General Theory of Phase Noise in Electrical Oscillators. IEEE J Solid-State Circuits, Volume 33, February 1998: 179-194. Frequency 10 kHz 100 kHz Simulated –60.9 dBc/Hz –86.97 dBc/Hz Measured –65 dBc/Hz –86 dBc/Hz Conclusion PLLs or frequency-locked loops (FLLs) are common in many types of communication circuitry including serial/deserialize (SERDES), clock recovery, data recovery, and LO frequency synthesis. As data rates for high-speed serial links rise to 40 GB/s and as RF wireless frequencies increase, the noise (phase or jitter) of a locked PLL/FLL and ﬁrst-order locked-loop performance must be designed to meet narrower phase-noise margins related to bit error rate (BER), packet error rate (PER), error vector magnitude (EVM), and dynamic range. When designing to these tighter speciﬁcations, the ability to characterize locked-loop circuit-level blocks and accurately assess the noise being introduced by these blocks in a closed-loop condition is extremely valuable. Meeting these speciﬁcations is critical to the creation of successful ﬁrst-pass product designs that provide lower engineering and manufacturing costs. This is especially true at the IC level because the initial manufacturing costs tend to be very high. 4. Demir, A., Mehtotha, A. and Roychowdhury, J. 1999. Phase Noise in Oscillators: A Unifying Theory and Numerical Methods for Characterization. IEEE Trans. Circuits Syst. II, Volume 46, Jan. 1999: 56-62. Agilent Measurement Journal 49 http://www.planetanalog.com

Table of Contents Feed for the Digital Edition of Agilent Measurement Journal - Issue 5 - 2008

Agilent Measurement Journal Issue 5 Finding a New Path when Assumptions Break Down Contents Testing MIPI D-PHY Protocols Oscilloscope Firmware Update DNA Replication Joining the LTE/SAE Trial Initiative Testing Proteins Praise for DC Power Analyzer Scripting Features for AMDS Testing Hybrid PCBA Systems Improving the Gene Expression System Workflow Turning a “Good Enough” Test Strategy into One That’s Reliable, Repeatable and Traceable Understanding the Effects of Limited-Bandwidth Channels on Digital Data Signals Introducing the 3GPP LTE Downlink Validating the 26 Validating the Physical and Protocol Layers in DDR Memory Interfaces Understanding Total Jitter Measurements of Low Probabilities Using Behavioral-Model Simulation to Accurately Predict First-Order PLL Performance Creating Synchronous High-Frequency Sampling across Multiple Digitizers Overcoming the Challenges of Testing FlexRay Networks Understanding Operating Life and Repeatability of Electromechanical Switches and their Effect on Total Cost of Ownership Implementing Micro and Nano LC/MS Techniques for High Sensitivity Lipidomics Analysis

Agilent Measurement Journal - Issue 5 - 2008

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