Agilent Measurement Journal - Issue 5 - 2008 - (Page 51)

Achieving synchronous sampling T Today, high-speed digitizer systems operating at well above 100 MSa/s are being used in a diverse range of applications: operation of single-pulse linear induction accelerators for ﬂash radiographic facilities, hypervelocity ballistic-range experiments, propulsion research, and more. A growing number of such applications require simultaneous measurement of high-frequency signals over many channels. Most of today’s high-speed digitizers or oscilloscopes feature a maximum of only four channels. For applications requiring more than four channels — and needing very precise time correlation between channels or accurate phase of continuous signals — it is necessary to synchronize the sampling clocks of multiple instruments. Accurate time correlation requires synchronous sampling across multiple digitizers and multiple channels.2 This can be required when analyzing multi-channel single-shot events, for example, or when digital signal processing (DSP) operations combine samples from different signal channels before processing the data. Although it is possible to achieve multi-channel synchronous sampling by distributing a common sampling clock to the various modules, this presents a major technical challenge at high frequencies. As one example, the backplane busses and connectors used in CompactPCI/PXI chassis are not well suited to high-frequency signals, and above about 100 MHz, clockpulse edges deteriorate signiﬁcantly and induce jitter. Using coaxial cables and proper connectors requires costly high-frequency fan-outs. Another way to achieve synchronous sampling is to lock each digitizer’s sample-clock generator to a common high-stability 10-MHz reference signal. By feeding the frequency reference to every module, the “sampling instants” on all channels will be synchronous (e.g., the sampling-clock delay between any two channels will be constant). The sampling-clock delay includes all delays due to factors such as delay lines, signal path lengths and cable lengths (for the 10-MHz frequency reference). To verify that the criteria for synchronous sampling are satisﬁed, this delay must be shown to be constant. The sampling instants ti are equally spaced (within the clock jitter) and have an interval equal to the inverse of the sampling frequency. With constant sampling-clock delay, the waveform data can be resampled using interpolation to yield a waveform with samples taken at exactly the same instants as the chosen reference channel. In cases that require data from several channels to be combined in DSP operations, it may be necessary to measure the sampling-clock delay to allow data resampling. With Agilent Acqiris digitizers, synchronous sampling can be achieved across several modules with ASBus, a bus system that distributes trigger and clock signals.1 Up to seven modules can be connected with ASBus; however, by distributing a common, high-stability 10-MHz clock reference to all digitizers, it is possible to easily achieve synchronous sampling across a greater number of acquisition channels. One important challenge remains: measuring sub-nanosecond time delays between the synchronous samples of different channels. This article presents a method for measuring sampling-clock delay using the acquired signal as a time reference. 1. ASBus is a proprietary high-bandwidth auto-synchronous bus system that allows distribution of all necessary trigger and clock signals across up to seven digitizer modules. 2. Throughout this article, synchronous sampling is deﬁned as follows: For any two channels A and B acquiring data in synchronous sampling mode, and where the ith voltage sample uAi is the measured signal voltage on channel A at time ti, there is a corresponding sample uBj measured on channel B at time tj = ti+ DAB. DAB is the sampling-clock delay of B with respect to A and is constant over all i values. Agilent Measurement Journal 51

Table of Contents Feed for the Digital Edition of Agilent Measurement Journal - Issue 5 - 2008

Agilent Measurement Journal Issue 5 Finding a New Path when Assumptions Break Down Contents Testing MIPI D-PHY Protocols Oscilloscope Firmware Update DNA Replication Joining the LTE/SAE Trial Initiative Testing Proteins Praise for DC Power Analyzer Scripting Features for AMDS Testing Hybrid PCBA Systems Improving the Gene Expression System Workflow Turning a “Good Enough” Test Strategy into One That’s Reliable, Repeatable and Traceable Understanding the Effects of Limited-Bandwidth Channels on Digital Data Signals Introducing the 3GPP LTE Downlink Validating the 26 Validating the Physical and Protocol Layers in DDR Memory Interfaces Understanding Total Jitter Measurements of Low Probabilities Using Behavioral-Model Simulation to Accurately Predict First-Order PLL Performance Creating Synchronous High-Frequency Sampling across Multiple Digitizers Overcoming the Challenges of Testing FlexRay Networks Understanding Operating Life and Repeatability of Electromechanical Switches and their Effect on Total Cost of Ownership Implementing Micro and Nano LC/MS Techniques for High Sensitivity Lipidomics Analysis

Agilent Measurement Journal - Issue 5 - 2008

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