Agilent Measurement Journal - Issue 5 - 2008 - (Page 54)

The sine wave signal providing the time reference was produced by an Agilent synthesized signal generator. The signal amplitude was adjusted to be about 80 percent of full-scale input. To ensure the same signal was being fed into both channels, a 50 Ohm passive splitter was used to connect two cables of identical length. A similar splitter and identical length cables were used with an Agilent 33220A function/arbitrary waveform generator to provide a trigger pulse. The digitizers were controlled through a MATLAB script. Care must be taken to ensure that both digitizers are armed and ready before a trigger pulse is sent, preferably by controlling the 33220A with the MATLAB script. ® Results: Sampling-clock delay A series of one million measurements was performed at 400 MSa/s. Each acquisition was 2,048 samples long, and the sine-wave signal frequency was set to 25.048828125 MHz. Figure 3 shows a histogram of the measured sampling-clock delay: The mean value is 1.115 ns and the standard deviation is 3.475 ps. 3.5 3 2.5 x 104 2 Sampling-clock delay histogram Standard deviation 1.878 ps 100 k measurements 6000 4000 2000 0 1.11 1.095 1.115 ns 1.1 1.12 1.105 1.11 ns 1.115 1.12 1.125 1.13 1.5 1 0.5 Results: Synchronization states When synchronizing the sampling clock generators with a common 10-MHz reference, several effects come into play that produce multiple possible synchronization states. The ﬁrst is linked to the actual hardware implementation of the samplingclock generator. In the case of Agilent Acqiris digitizers, six possible states are especially interesting: two are one-half of a sampling interval apart at the maximum sampling rate of 400 MSa/s and the other four are one-quarter of a sampling interval apart at 200 MSa/s. When decimation is used to achieve lower sampling frequencies, additional sampling-clock delay states may be created through the initial state of the decimation counter.5 These must be taken into account when comparing the results of sampling-clock delay measurements. When the sampling frequency is set, the digitizer clock generator settles into one of the possible states due to the ﬁrst effect described above. It remains locked in that state for all further acquisitions, until the registers controlling the clock generator are reloaded. The latter occurs either when a full self-calibration is performed or when the sampling frequency is changed. The state multiplication effect due to decimation, however, is always effective (the decimation counter is reset at the beginning of each acquisition). A series of measurements at 400 MSa/s, 200 MSa/s and 100 MSa/s veriﬁed that the state was indeed conserved within a calibration epoch (unless decimation was active). 0 1.09 Figure 3. This histogram of the measured sampling-clock delay has a mean value of 1.115 ns and a standard deviation of 3.475 ps. It is worth noting that the standard deviation includes delay drift due to temperature variations that occurred during a 35-hour measurement in an uncontrolled environment. This is illustrated in Figure 4, which plots the measured delay for each of the one million measurements. The delay variation due to temperature was measured to be 10 ps/ºC. The sampling-clock delay variation with temperature was recorded over a period of about 14 hours (Figure 5). Over a short time period (e.g., 10,000 measurements) the typical standard deviation is reduced to about 2 ps. Sampling-clock delay 1.15 1.14 1.13 1.12 1.11 1.1 1.09 0 ns 2 4 6 x 105 acquisition 8 10 5. Decimation is the process of retaining only one of n samples to yield a lower effective sampling frequency than the sampling-clock oscillator can provide. Figure 4. The standard deviation of the sampling-clock delay includes delay drift caused by temperature variation during the 35-hour measurement. 54 Agilent Measurement Journal

Table of Contents Feed for the Digital Edition of Agilent Measurement Journal - Issue 5 - 2008

Agilent Measurement Journal Issue 5 Finding a New Path when Assumptions Break Down Contents Testing MIPI D-PHY Protocols Oscilloscope Firmware Update DNA Replication Joining the LTE/SAE Trial Initiative Testing Proteins Praise for DC Power Analyzer Scripting Features for AMDS Testing Hybrid PCBA Systems Improving the Gene Expression System Workflow Turning a “Good Enough” Test Strategy into One That’s Reliable, Repeatable and Traceable Understanding the Effects of Limited-Bandwidth Channels on Digital Data Signals Introducing the 3GPP LTE Downlink Validating the 26 Validating the Physical and Protocol Layers in DDR Memory Interfaces Understanding Total Jitter Measurements of Low Probabilities Using Behavioral-Model Simulation to Accurately Predict First-Order PLL Performance Creating Synchronous High-Frequency Sampling across Multiple Digitizers Overcoming the Challenges of Testing FlexRay Networks Understanding Operating Life and Repeatability of Electromechanical Switches and their Effect on Total Cost of Ownership Implementing Micro and Nano LC/MS Techniques for High Sensitivity Lipidomics Analysis

Agilent Measurement Journal - Issue 5 - 2008

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