Agilent Measurement Journal - Issue 5 - 2008 - (Page 58)

Node Host Host processor interface Communication controller Power supply Bus driver channel b Bus driver channel a While the FlexRay protocol offers deﬁnite beneﬁts and holds great promise for advanced automotive communications systems, it also presents some difﬁculties. Namely, in a FlexRay network, sporadic errors are very hard to ﬁnd and are often traced back to network communication issues. Recent studies have shown that errors in network communication are the number two cause of failures in automotive electronics and are among the highest-cost automobile repairs. The problem is further complicated by a design trend toward even more networking, which will result in higher complexity. The ability to ﬁnd network communication errors depends on the engineer ensuring the signal integrity of FlexRay signals as well as proper timing of the time-triggered communication bus. It also requires a quality metric speciﬁc to the FlexRay protocol. Channel a Channel b Examining the FlexRay quality metric The quality metric for networks based on complex protocols such as FlexRay must meet a few requirements. In the case of the FlexRay protocol, the quality metric has two individually observable measurements: physical layer quality and protocol layer quality. Metrics for each of these measurements are deﬁned as follows: Physical layer quality metric: This metric covers the quality of the network cabling and identiﬁes which impedance measurements exist at the various connectors, stubs and termination points. The FlexRay physical layer measurement of robustness is based on the collection of all measured electrical characteristics shown to be in accordance with design speciﬁcations. This quality measurement demonstrates if design parameters are obeyed and, subsequently, the achieved degree of quality. Protocol layer quality metric: This metric covers the higher levels of the protocol, highlighting such problems as semantics, incorrect packet data and incorrect cyclic redundancy check (CRC) values. Timing dependencies are also observed, for instance, to check the update intervals of signals or sequences of events. Such timing errors or race conditions can produce errors that are very hard to reproduce: From an electrical point of view, the system may work perfectly; however, communication errors may still occur and the system will not behave as planned. Figure 1. The FlexRay block diagram. The FlexRay protocol is composed of both static (ST) and dynamic (DYN) segments arranged to form a periodically repeated bus cycle. The ST segment employs a generalized time-division multiple-access (GTDMA) scheme. In contrast, the DYN segment uses a ﬂexible TDMA (FTDMA) bus-access scheme (Figure 2). FlexRay provides scalable (e.g., single- or dual-channel) static and dynamic message transmission and incorporates the advantages of familiar synchronous and asynchronous protocols. It supports collision-free bus access, fault-tolerant clock synchronization through a global time base, and guaranteed message latency with message-oriented addressing occurring through identiﬁers. FlexRay has an error-management service that provides error handling and error signaling, a wakeup service that addresses the automotive system’s powermanagement needs, and a diagnosis service that tests the bus guardian on the physical layer. 58 Agilent Measurement Journal

Table of Contents Feed for the Digital Edition of Agilent Measurement Journal - Issue 5 - 2008

Agilent Measurement Journal Issue 5 Finding a New Path when Assumptions Break Down Contents Testing MIPI D-PHY Protocols Oscilloscope Firmware Update DNA Replication Joining the LTE/SAE Trial Initiative Testing Proteins Praise for DC Power Analyzer Scripting Features for AMDS Testing Hybrid PCBA Systems Improving the Gene Expression System Workflow Turning a “Good Enough” Test Strategy into One That’s Reliable, Repeatable and Traceable Understanding the Effects of Limited-Bandwidth Channels on Digital Data Signals Introducing the 3GPP LTE Downlink Validating the 26 Validating the Physical and Protocol Layers in DDR Memory Interfaces Understanding Total Jitter Measurements of Low Probabilities Using Behavioral-Model Simulation to Accurately Predict First-Order PLL Performance Creating Synchronous High-Frequency Sampling across Multiple Digitizers Overcoming the Challenges of Testing FlexRay Networks Understanding Operating Life and Repeatability of Electromechanical Switches and their Effect on Total Cost of Ownership Implementing Micro and Nano LC/MS Techniques for High Sensitivity Lipidomics Analysis

Agilent Measurement Journal - Issue 5 - 2008

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