CircuiTree - July 2008 - (Page 19)

[ Tech Talk ] rier against PEG adsorption. The slower diffusing PEG slowly builds up on the upper part of the hole wall near the surface, acting as a plating inhibitor while the dominant SPS at the bottom of the hole accelerates plating. Figure 4 illustrates the additive distribution as a function of via depth position very early in the plating cycle. The red spheres symbolize SPS and the green spheres symbolize PEG. Landau found that the relative concentrations of PEG and SPS have an inﬂuence on how well the bottom-up plating performs. His ﬁndings also explain the effect of via diameter and aspect ratio on the bottom-up plating performance (Figure 3). Wider via diameters mean a less favorable volume to area ratio in the hole, meaning there is more PEG initially available to adsorb on the via bottom. A high aspect ratio via results in a greater concentration gradient in the hole cylinder between a slowly diffusing additive such as PEG and a faster diffusing additive such as SPS, thus favoring bottom-up plating. optimizing the plating bath composition and the waveform, much improved results were obtained. (or de-plating or corrosion) of metal from a metal surface that forms the anode of a cell whereby metal is removed faster from surface protrusions than from valleys so that the result is a smoother surface. Venkatachalam11 showed that surfaces get even smoother if a pulsated direct current is employed. Buhlert and others found that this method can further be reﬁned by selecting speciﬁc impulse times and current densities as well as speciﬁc pulse frequencies.12 ■ References 1. Wiedmann, W., et al., “Badregeneration von Puls-Kupferbaedern in der Leiterplattenfertigung mittles UV-Recycling,” Procuktion von Leiterplatten und Systemen (PLUS), 7/ 2006. 2. Garich, H. M., et al., “In-Process Recycling of Rinse Water From Copper Plating Operations Using Electrical Remediation,” Plating & Surface Finishing, April 2004. 3. Kenny, S., “Blind Micro Via and Through-Hole Filling for Thin Core and Flexible Base Materials,” The Board Authority, 2006. 4. Landau, U., Malyshev, E., Akolkar, R., and Chivilikhin, S., “Simulations of ‘Bottom-Up’ Fill in Via Plating of Semiconductor Interconnects,” Paper 189 d, Session TK, Proceedings of the AIChE Annual Meeting, San-Francisco, 2003. 5. Landau, U., “Metallization of Submicron Features in High-End Semiconductor Devices by Copper Electroplating,” Invited Seminar, Energizer, Westlake, Ohio, 2005. 6. Lefebvre, M., and Allardyce, G., et al., “Copper Electroplating Technology for Microvia Filling,” Circuit World, 29/2 (2003). 7. Dietz, K., “Fine Lines in High Yields (Part LIV): Organics in Copper Plating Baths (Part A),” CircuiTree, Feb. 2000. 8. Dietz, K., “Fine Lines in High Yields (Part LV): Organics in Copper Plating Baths (Part B),” CircuiTree, March 2000. 9. Kim, B., et al., “Back-End Copper Plating for 3D and Wafer Level Packaging Applications,” Proceedings, 3D/SiP Advanced Packaging Symposium, Research Triangle Park, N.C., 2007. 10. Huang, M., et al., “Study on Copper Pillar Interconnect for Flip-Chip-on Module Packages,” Proceedings, 3D/SiP Advanced Packaging Symposium, Research Triangle Park, N.C., 2007. 11. Venkatachalam, R., et al., “Electropolishing of Stainless Steel Using Pulse Technique,” Transactions of the Metal Finishers Association of India, Vol. 1, 1992, No. 4. 12. Buhlert, M., et al., “The Advantage of Electropolishing With Pulsed Direct Current,” The Journal (Photochemical Machining Institute), December 2004. Figure 5 Improvements in BottomUp Plating By Bath Composition and Waveform Selection (Source: Bioh Kim, Semitool) The challenge is void-free plating without reducing the current density unduly so that productivity is maintained. Copper Pillar Plating Wafers are typically bumped by plating solder, stenciling solder, or solder ball placement. These techniques all involve a reﬂow step that results in a sphere-shaped bump so that for a given, desired stand-off height the pitch will be limited because the bumps are basically as wide as they are high. Copper pillars, on the other hand, are plated, capped with tin, nickel/gold, or tin/silver, but don’t go through a reﬂow process so that they remain pillar shaped and allow ﬁner pitch.6,10 Copper pillars also have the added advantage of better thermal and electrical conductivity. Figure 4 Additives Distribution in a Blind Via (Courtesy of U. Landau) Electropolishing Through-Silicon Vias TSVs enable the z-axis interconnection of 3D die stacks. There are several TSV processes, typically distinguished by the processing sequence (via ﬁrst and via last processes) and the conductive interconnect material used, such as polysilicon, tungsten, or copper. The copper is electroplated into a very high aspect ratio blind via that is either etched or laser drilled into the wafer and covered with a seed layer. After bottom-up via ﬁll plating, the wafer is back-ground to the bottom of the blind via to expose the copper. The via ﬁll plating performance is inﬂuenced by a number of factors.9 A nonoptimized plating bath resulted in current crowding near the via opening and premature closing at the top of the via, leaving a void (see Figure 5). After Electropolishing is, of course, the opposite of plating and one could argue that it does not belong in an article on plating. Electropolishing is the electrochemical removal Karl H. Dietz is CircuiTree’s technical editor. Email karl.h.dietz@USA.dupont.com Figure 6 Schematic of a Copper Pillar Interconnection (Source: Mark Huang, Micron) circuitree.com • July 2008 19 http://circuitree.com

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CircuiTree - July 2008 Contents My Line Industry Review Tech Talk Flexible Thinking Toward a PCB Production Floor Metric for Go/No Go Testing of Lossy High-Speed Transmission Lines Intelligent Design 20-Year Retrospective Ask the Flexperts Environmentally Speaking BPA Growth Curves Considering Design Variants to Maximize Process Efficiency Market Outlook Technical Product Spotlights Classified Ads Upcoming Events Ad Index

CircuiTree - July 2008

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