CircuiTree - September 2008 - (Page 43)

means to increase part density and even stacked dies are sometimes used on PCBs. Sequential buildup technology, stacked, ﬁlled vias, and ultra-HDI are also technologies that were must-haves in packaging design and are now being applied in a larger scale to dramatically increase the wiring density at the PCB level. In the packaging industry, the same technologies became a requirement early on as the silicon roadmaps showed a faster growth in chip I/O density than the existing substrate technologies could support. The extreme would be to not have a package but design a full board with bare dice utilizing package substrate technology. This is done today but the cost is higher than for traditional technologies so currently it’s not widespread. Will that change? Maybe! Probably! Unfortunately, the use of such technologies is driven by business drivers not by its coolness factor. For markets where this level of integration is needed, it’s already in use. While extreme technology used to be driven by military and aerospace markets, we have for the last couple of years seen a shift where some of the most advanced technology is being driven by the consumer markets’ constant urge for faster, more, smaller, and cheaper. This shift is a major event in that the production volumes become many orders of magnitude larger while price and time to market is of the essence, thus driving the introduction of advanced substrates for system use. comes to completing the full board system within specs. This is even worse for chip sets where signals to be connected can be located on opposite sides of the packages. Chip-Package-PCB Co-Design For today’s complex multi-technology boards, chip-package co-design does not sufﬁce. We need chip-package-PCB co-design. While this is rather new in the industry, a similar process has been used for FPGA packages for some time. The signal pin allocation for FPGAs can be controlled by its designer, so by analyzing the PCB interconnects and determining an optimal pin allocation, the updated allocation can be sent to the FPGA design tool. The result is shorter signal traces and fewer via holes, leading to higher completion rates and higher performance. In chip-package-PCB co-design we need to do the same for chip packages: we need to change the package signal allocation while considering the PCB onto which the package will go. There are just a few problems associated with that: • The PCB design may not even have started; and • The package itself can be intended for open market sale—who knows what the PCB will look like. Virtual Prototyping This leads us to virtual prototyping. With this technique, we use the design data we do know, in combination with assumptions regarding design data as yet unknown to us, to build a temporary mockup of the PCB and use that to optimize the PCB-to-package interconnects. Clearly, the further down the design ﬂow we go, the more actual design data becomes available and we can replace assumptions with real data and re-run the optimization. The gain of virtual prototyping becomes obvious if you are familiar with the costs involved to do changes to a chip design once it has been completed. These costs are astronomical and often so high that a change cannot even be up for discussion and one has to live with the circuit as is, or even cancel the project. The opposite is true very early in the design cycle. At the virtual prototyping stage, it is so early in the cycle that even dramatic changes to the design can be made at virtually no cost, and this is a fact we must make use of. Having optimized the package pinout so that the interconnects on the PCB leading to the package can be implemented, the next step is to optimize the chip I/O to the now-ﬁxed package pinout. This step most likely leads to changes in the chip I/O design and if made after design completion would be too expensive. In a virtual prototyping ﬂow, these assignments and optimizations can start so early that chip, package, and board are virtual and continue throughout the design process. This allows chip, package, and PCB to be in ﬂux until an optimal solution is ﬁnalized. Obviously, in that process, the early virtual data must be gradually replaced with actual design data to allow the design to converge toward an optimum completion. To make matters even worse, each package can have multiple dies and other bare or packaged parts of mixed technology—for example an SiP/SoP with multiple ASICS in combination with ﬁxed IP circuits such as standard memories. Different package technology such as package-on-package also adds a new dimension to the design. Design teams early realized this need and most companies developed systems based on spreadsheets or ASCII ﬁles to manually perform this step. Figure 1 shows the typical set of spreadsheets used to circuitree.com • September 2008 43 Methodology Convergence There is another view to consider as well: design methodology. Traditionally, chip, package, and PCB were all designed separately and completely isolated from each other. Separate teams each completed their piece with little if any interaction in between the teams. With ultra high-speed circuits, RF modules, and sometimes I/O counts in the thousands, it is no longer possible to design chip and package separate from each other. The location of the die in the package and even the location of speciﬁc I/O signals on a chip have a profound impact on the package. Locations of power and ground cells are also critical as modern lowvoltage designs also have low noise margins. It’s easy to take a perfectly performing piece of silicon and completely ruin its performance with a poor package design. The same can happen on a PCB: the package is connected in such way that the system fails to operate. It used to be that in this case, the PCB designers were (unfairly) blamed for doing a poor design as the chip clearly worked and so did the package. Today, the margins are so small that unless the entire interconnect from chip to package to board—all the way to the next package—is arbitrated among all three, you may end up with a package that really can’t be routed on the board without disturbing the signal integrity. Chip-Package Co-Design The industry’s solution to the dilemma was chip-package co-design: designing the chip while taking the package design into account. Signals, power, and ground are assigned to the package pins and the connectivity to the die is analyzed. If needed, the I/O cells are relocated to create an optimal chip-package system. Hopefully you have already noticed that something is missing in the picture: there is no PCB! There is not a PCB designer alive that hasn’t frequently cursed those package designers and their choice of package pinout, as it leaves the PCB designer with severe difﬁculties when it http://circuitree.com

Table of Contents Feed for the Digital Edition of CircuiTree - September 2008

CircuiTree - September 2008 Contents My Line Industry Review Tech Talk Flexible Thinking New Halogen-Free Materials: Their Time Has Finally Arrived Asian Section IPC Issues PCB and Package Convergence Ask the Flexperts Market Outlook IPCA Showcase Technical Product Spotlights Classified Ads Upcoming Events Ad Index

CircuiTree - September 2008

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