CircuiTree - December 2008 - (Page 42) Designing for Signal Visibility in Backplanes and Serial Links Juan Garza S ignal integrity in the design of backplanes and multigigabit serial links has become one of the most vexing problems in high-speed digital design. As aggregate backplane speeds exceeded 1 and 2.5 Gbits/sec in the early 21st century, designers learned that problems in planning for timing skew and trace analysis increased exponentially from slower designs. In recent years, 10 Gbit/sec Ethernet emerged as a common standard in both backplane and serial-link development, with plans for 40 and 100 Gbit follow-ons. Developers in both backplane and short-range fiber link designs have relied on physical probes and behavioral simulation to gain a necessarily limited view of signal characteristics. While test equipment companies are making every effort to increase the speed of probes into tens of gigabits per second, testing at speed has become problematic, while behavioral simulation of such high-speed links sacrifices accuracy. The utility of adding bit-compare circuitry to I/O devices is one means of overcoming incomplete signal information. When a waveform can be accessed after equalization and before digital bit-stream conversion, as a regular hardware element of a clocking or errorcorrection chip, signal analysis can be performed much easier than in a testbed with a physical probe. Introduction Commoditizing high-speed serial links would not have been possible without the advances made in the last decade in high-speed equalization and dispersion compensation. In particular, the embedding of dispersion-compensating equalizers directly into receivers allowed error-free signals to be received from a transmission noisy enough to display an eye diagram that was all but closed. Embedded equalization, however, means a receiver’s output is no longer available for analysis. Further digitization of the receiver chain and use of nonlinear equalization may all but obsolete the traditional oscilloscope. Without embedded support for signal visibility within receiver chips, developers may be forced to rely on traffic-generation and simulation products from the test community, which provide, at best, a partial analysis of signals based on simulated traffic rather than real-time data. The move by test equipment manufacturers to develop golden 42 December 2008 • circuitree.com simulation models for receiver front-ends can be attributed, in part, to the declining utility of eye diagrams. Traditionally, the hexagonal region of an eye mask provided the time and amplitude parameters within which acceptable bit-error-rate performance could be expected. But as equalization methods improved at the same time serial speeds approached 10 Gbits/sec and greater, the assumption that recoverable signals required open eyes no longer held. At present, significantly degraded eye diagram displays can still recover acceptable signals. As DSP methods for equalization improve, eye masks indistinguishable from noise still may offer recoverable signals. Test equipment companies have sought to augment software-only solutions with in situ probes, though high-speed serial links and backplanes have difficult hurdles to overcome. Any type of probe, even a passive device, adds capacitive loading to a system, and an active probe can have direct impact on available bandwidth. An oscilloscope cannot be used in place of the receiver device when traffic is present, as it opens the communication loop. In an effort not to obsolete their equipment, manufacturers of oscilloscopes have offered many software packages to approximate the post-equalization waveform by emulating the receiver equalization. The continued improvement of simulation models can make such emulation methods useful, but it is important to emphasize that such methods do not view the true signal. Instead of working against the trends for better on-chip signal processing, we propose a means of taking advantage of trends in VLSI integration, signal processing, and real-time signal analysis. By integrating circuitry on a transceiver chip that allows direct scanning of the data eye, a data stream can be output that is representative of the input waveform. The evolution of such bit-compare architectures has allowed the implantation of the architecture on a per-pin basis. The prototype design is advanced enough to allow for implementation of a real-time architecture that can eliminate the need for probes, while providing full access to signal characteristics within a serial data path. On-Chip Adaptive Sampling Luckily, the ability to embed signal analysis within a high-speed communications chip does not require any breakthroughs in design. By 44 http://www.circuitree.com
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