CircuiTree - December 2008 - (Page 44) Designing for Signal Visibility in Backplanes and Serial Links applying existing clock and data recovery (CDR) circuits with new sampling methods, specialized circuit blocks can be implemented to sample signals on a per-pin basis. The method uses the same channels for receiving data and scanning data. This not only assures accurate real-time analysis of the signal but carries fringe benefits of reducing overall power dissipation on the receiver chip and reducing overall complexity of the design. Why locate the scan at the CDR? This is precisely where postequalization signals transfer from analog to digital domain and is the unique place in the system design where tuning information from CDR and voltage information are both present. As long as the CDR can provide information to a sampling flip-flop, a variety of CDR architectures can be used for a scanning task, allowing the CDR to be tailored to the particular receiver application. The only requirement for the design is that the phase-locked loop at the core of the CDR be able to extract a clock signal with low jitter and high loop bandwidth, while working independently of the clocking function. In one optimal design, the receiver itself is implemented as a programmable variable-gain amplifier. Because the gain of the receiver is programmable, input signal strength can be controlled, improving waveform scanning. Programmability also allows better control of peak-to-peak voltages, preventing clipping of the p-p voltage swing. If the variable voltage threshold is programmed into the sampling flip-flop or the input receiver, a digital-analog converter (DAC) can be used to apply a controlled offset to the slicing function. Notice that a high-resolution DAC is not required—between six and eight bits represents a reasonable compromise between resolution and accuracy. Various synchronous and asynchronous design alternatives are possible. For example, if a swept sampling time is desired, a variable phase-delay circuit could be inserted in the clock path to the flip-flop. The variable time delay could be based on the clock rate of the data and split a complete clock cycle into a uniform array of phase steps. Asynchronous alternatives could be implemented, provided there is sufficient dynamic range at the lowest operating frequency. Critical to the implementation of a bit-compare sampling architecture is the implementation of a second parallel channel, connected to the same input source, but independently adjustable from the first channel. This duplicates the sampling capability of the core design and allows two samples of the input signal to be obtained from two different voltage and phase positions. One clock source is used for both channels, establishing a common timing reference for both channels. The circuitry in the second channel can be powered down when scanning is not taking place to lower overall power dissipation. The parallel channel gives the scanning circuitry the capability of a bit-error-rate detector. The two results from the parallel sampling channels corrected for skew and compared on a bit-by-bit basis. When the designer sets a particular time period and accumulates results over that period, results are similar to a BERT output. Typical accumulation periods are greater than 2(16) (65,536) data bit periods to provide sufficient averaging and error rate resolution. Using Embedded Scan to Observe Signals The dual-channel sampling is particularly useful in comparing a reference sample to a swept sample. The hold/sample method entails holding one of the samples in the center of the eye diagram as a reference while scanning the other channel. By keeping the reference signal in an optimal position, the live data stream can be placed in the position with the lowest possible data rate. When the roaming channel has completed its scan, it can return to the optimal position for that channel to sample the data with the lowest possible BER. The scanning channel may optimize to a slightly different position due to the vagaries of transistor matching. Designers could use a multiplexer circuit to switch between the two sampled channels, allowing the channel that was carrying live data to perform a scan while the channel that was scanned originally carries live data. This alternating scan method allows the eye diagram to be continuously scanned, even while carrying data on the eye waveform. Through such continuous scanning, the dual channels can continuously track the optimal position in the eye diagram, even as it drifts or fades. The rate of disagreement between the two channels is equivalent to BER, and this rate will increase as the swept signal crosses signal edges in the data stream. The BER for any location across the eye depends on the type of data and the scrambling method used. Purely random data will toggle with even probability for each consecutive bit. Coding methods will alter the probability to reduce the run length of consecutive identical digits. It’s important to emphasize the flexibility of having two independently controlled channels. The simplest scanning involves measuring either or both channels evenly across the voltage or phase array, but the shape of the data eye may dictate a special algorithm for scanning. This can give rise to an adaptive scanning process when adjusted over time. If a large number of voltage and phase conditions are tested, the BER count depth can itself become an important variable. For SONET (or even Ethernet) protection switching, real-time monitoring could be used. For a high-granularity level of detail, slower characterization also could be used. We are not limited to the two dimensions of data used in contour plots. On 3D graphs of phase, voltage, and BER count depth, for Figure 1 Placement of Embedded Waveform Viewing Function 44 December 2008 • circuitree.com Figure 2 Dual Sampling Embedded Waveform Viewing Architecture http://www.circuitree.com
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