CircuiTree - January 2009 - (Page 21) tion technology, this type of buried defect is not detected with AOI equipment. Case 2: Crack or Small Void Cracks or voids may occur where the via barrel plating is thin, as illustrated by the left side of Figure 3. Poor bonding between the bottom of the via and the target pad can result in a crack or void as illustrated in the right-hand example. The result is an unstable connection that is easily affected by temperature or mechanical force. These defects are invisible to AOI and difficult to detect reliably at final electrical test due to their intermittent behavior. Final electrical test systems apply substantial force to each connection via the spring probes that contact the product as shown in Figure 4. The accumulated pressure of multiple adjacent probes results in an extremely high compressive force, causing temporary contact such that the defect may pass final electrical test. A final test system with milliohm measurement ability could catch some additional defects in this scenario, but only in limited cases where the resulting contact is weak enough to fall into the detectable range of the system. The need for four wire Kelvin test probes conflicts with many HDI product geometries and often prohibits this technique. The limited number of defect detections from milliohm measurement would still come at the very end of the manufacturing process. Case 3: Latent Defect ages to include the value of expensive components added to the substrate, shipment, replacement cost, and loss of use. Because the mechanisms that produce this defect are similar or identical to those that produce the aforementioned more easily detected examples, a mechanism that detects high populations of any of these defect types can be useful as a process control alarm. The value of such an alarm is increased when it can be placed earlier in the manufacturing process. Automatic Electrical Inspection A new type of equipment is available to provide an automatic electrical inspection (AEI) process capable of verifying the electrical continuity of HDI and normal via barrels early in the manufacturing process, with minimum applied force. The AEI equipment would typically follow outer layer AOI and might be co-located with AOI equipment. But where AOI is purely an optical surface inspection, the AEI process measures the actual HDI network connectivity for all layers of the board, and does so with real resistance thresholds. No fixturing is required and the process occurs at rates equivalent to common AOI rates. (Note that with AEI there is no requirement to flip the panel as both sides are accessed simultaneously.) Also, the AEI method’s low false call rate minimizes added labor cost. As multilayer panels are processed rather than individual layers, only a small number of AEI machines are required (Figure 6). The AEI process does not replace final electrical test but provides an opportunity to screen for this defect type with reduced force applied to the panel and greater chance of detecting intermittent defects. As AEI occurs earlier in the manufacturing process, greater opportunity exists to adjust processes before additional defective panels are produced. AEI does not detect trace neck-downs and mouse-bites and would probably not replace AOI for individual layer inspection. AEI inspects panels that are laminated into their final stackup with outer layer traces formed and plated holes completed but prior to solder mask application or singulation/ subpanel formation. The test can also be performed on subpanels intended for sequential lamination with other subpanels. Less than one minute is required for a dual side scan of a full HDI panel. The machine requires no tooling or fixtures for different PCB part numbers or panel sizes. False calls are typically less than 2 per panel, an order of magnitude lower rate than is generally experienced with AOI. As the test is performed on full panels of the product, handling is minimized while throughput is maximized. AEI would probably not be used for individual inner layer inspection as these lack plated holes and inner layer connections. As only panels and subpanels are inspected, a substantially smaller number of AEI machines are required than is the case of AOI equipment. The ratio between required AEI and AOI machines is related to average layer count and the procircuitree.com • January 2009 21 Figure 4 Compression Force of Traditional Final Electrical Test Equipment Causes False Pass The potential for field or assembly failure exists in the example illustrated by Figure 5 where the via barrel plating is extremely thin but may maintain a connection through bare board manufacture. The metal is thin for only a short distance along the overall electrical signal path and may not have a measureable effect upon the total electrical resistance. Later the connection may fail entirely and abruptly. The same situation exists for partially formed voids between the via base and the target pad, as illustrated in Figure 3. Failure may occur when the substrate is exposed to the high temperature of reflow soldering, a risk increased by the higher temperatures employed with lead-free solders. In some cases, the product may reach the field and fail due to thermal, mechanical, or electrical current stress during operation. This type of defect is potentially the most expensive. The assembler or end-use customer may demand consequential dam- Figure 5 Thin Via Wall May Provide Solid Electrical Contact During Manufacturing but May Fail Due to Thermal or Mechanical Stresses of Assembly or During End Use Figure 6 AEI Scanning Equipment http://www.circuitree.com
For optimal viewing of this digital publication, please enable JavaScript and then refresh the page. If you would like to try to load the digital publication without using Flash Player detection, please click here.