CircuiTree - March 2009 - (Page 22) Minimizing Impedance Discontinuities in HighSpeed PCB Designs Cuong Nguyen and Leonard Dieguez A growing number of high-speed standards and proprietary serial protocols are posing major design layout challenges for PCB designers. These serial standards include PCI Express, Serial RapidIO, Gigabit Ethernet, XAUI/HiGig, SONET, CPRI, OBSAI, and a host of others. Serial buses with differential signaling are quickly replacing parallel buses as the demand for high-speed PCB designs increases. Differential signaling uses two output drivers to drive two independent transmission lines. One carries one bit; the other, its complement. The difference of the two signals measured between the two traces carries the information. A differential pair is a pair of transmission lines with some amount of coupling between the two legs of the pair. Differential signaling is especially vital in high bandwidth, highdensity hardware systems where very low error-rate data links are required. It provides critically needed immunity to common-mode electrical noise that is present at significant levels in most application systems. For example, using differential signaling avoids the classic ground bounce noise problem that is experienced with many high density ICs that use single-ended interfaces. It also provides higher noise margins that lead to lower bit-error rates in digital data links. As the edge rates of signals have increased due to the need to support higher bandwidths, another need for PCB design is to provide return paths for the inductive coupled current of the PCB. Differential signaling helps reduce the bounce seen from this inductive current because the current remains localized. This is due to the fact that as one of the leads of the differential pair is sinking, the other is sourcing current, essentially canceling the inductive influences. These high-speed serial buses demand transceivers that perform as output drivers to efficiently drive these protocols’ Gbps rates. Figure 1 FPGA Embedded Transceiver Block Diagram 22 March 2009 • circuitree.com Figure 2 High-Level Block Diagram of PCI Express Hard IP Block in an Advanced FPGA http://www.circuitree.com
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