CircuiTree - April 2009 - (Page 26)

i-Line UV Lithography and Sub-10μm Feature Size Package Substrate Technologies the dominating process for the image formation in the packing and PWB industry. The resolution of line and space (L/S) is related to the ﬁlm thickness. In general, the minimum L/S that can be formed is about 1.2~1.5 times the thickness of the resist in a manufacturing environment and down to 0.7~1.0 in the laboratory. The thinnest dry ﬁlm photo resist that is currently provided at production volume is 15µm (0.6mil). Therefore, the ﬁnest circuit traces that can be fabricated by using dry ﬁlm photo resist is about 18µm to 22µm in production and 10µm to 15µm in the laboratory. The ﬁnest photo resist lines and spaces on clad copper foil we achieved is 8µm. Liquid photo resist has higher imaging resolution ability and can be formed in any thickness. As the advanced package moves towards higher pin count, ﬁner pitch, and thinner proﬁle, liquid photo resist technology should be used. As the stripes of photo resist are getting ﬁner, the adhesion becomes weaker. A photo resist adhesion promoter is needed. formation, photo resist application, UV exposure, development, and electrolytic plating. After copper is plated, the photo resist is stripped away and the seed layer is etched off. This technology is currently predominantly used in high density package substrate and to some extent in the PCB industry. The method SAP-II has the advantages of achieving ﬁner copper lines and spaces and higher trace deﬁnition since only about half a micron of copper needs to be removed. The minimum line width and space achieved depends on the performance of the photo resists and the quality of process controls. Sub-10µm Feature Size Circuitry Technologies We have produced 10µm copper lines and 10µm spaces by using dry ﬁlm photo resist in the PRC Next Generation Substrate Laboratory. Figure 9 shows four pairs of copper traces with lines and spaces of 10, 15, 20, and 25µm on ABF/BT substrate by using dry ﬁlm photo resist. Metallization Two types of processes that are typically used for metallization are subtractive and additive. The subtractive process utilizes chemical solution to etch copper away through open areas of photo resist to form the circuitry. Figure 8 shows subtractively etched 20µm lines and spaces on 12µm clad copper foil on BT laminate board. Note that the etched copper traces have almost vertical walls and equal line width and space width. Further reduction of the copper line width is limited by the roughness of the bottom surface of the copper foil (see Figure 8). The additive process utilizes electrolytic plating to ﬁll copper in the patterned photo resist (pattern plating). Electrolytic plating requires a thin conductive layer as electrode, called seed layer. There are two ways to provide the electrode: (I) a very thin copper foil, say 3µm, using resin coated copper (RCC) technology, or (II) electroless plated copper (~0.5µm thick) on resin. These kinds of additive processes, I and II, actually are semi-additive process (SAP). The SAP consists of dielectric ﬁlm surface treatment, a thin layer of conductive layer (seed layer) Fig 10 Ultra-Fine Line Routing on ABF Buildup for Flip Chip With 100µm Pitch. Bonding Pad Size is 40µm. Line and Space is 8.6µm. Three L ines a re R outed i n a Pi tch. Co pper T hickness i s 8 .5µm. Routing capability: Four Rows Per Pitch and 10,000 Pads/cm2 Fig 9 Pla ted C opper Traces With Line Widths and Spac e Widths of 10/15/20/25µm on ABF/B T b y U sing Dr y F ilm Photo Resist. The Copper Thickness Measured is 18µm. Table 1 Fabricated and Calculated L/Smin on 8μm-Thick Photo Resist in Proximity Mode Lithography Table 2 Fine Line Categories and Technologies L/S, µm <50 <25 Technology Fine Line Very Fine Line Ultra Fine Line Extreme Fine line Method Laminate Build Up Thin film Build-up Ultra thin film Resist Dry Film Dry Film Dry Film / Liquid Liquid Metallization Subtractive /SAP Subtractive /SAP Subtractive /SAP SAP Gap d, µm Thickness T, µm 90 8.0 60 30 0 Fabricated Lmin, µm 12 Calculated Lmin, µm 8.9 26 April 2009 • circuitree.com 10 7.2 7 5.3 5 2 <15 <10 http://www.circuitree.com

Table of Contents Feed for the Digital Edition of CircuiTree - April 2009

CircuiTree - April 2009 Contents Lead Wire The Wire Tech Talk Flexible Thinking New GUI Improves Time to Market for Serial RapidIO System Designs Environmentally Speaking Intelligent Design i-Line UV Lithography and Sub-10μm Feature Size Package Substrate Technologies Guest Column BPA Growth Curves Market Outlook Technical Product Spotlights Classified Ads Upcoming Events Ad Index

CircuiTree - April 2009

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