Dr. Dobb's Journal - June 2008 - (Page 38)

d06cass_p4ds 4/11/08 11:00 AM Page 38 State of the Art SOFTWARE TO HARDWARE PARALLELIZATION continued from page 36 When performing numerical calculations, you should track the precision of the variables that really need to be implemented—you may not always need the full precision of single- or double-precision floatingpoint data types for every variable. A fixedpoint multiplier and arithmetic unit combination usually requires less logic and, thus, more elements can be configured on an FPGA. The more elements, the more computations per cycle, and the faster the algorithm can execute. In FPGAs, integer or fixed-point math can often run 10 to 100 times faster than floating-point computations. To parallelize the algorithms, you must first perform a data-flow, which helps you understand how data moves between the different logic and computational elements. Next, execute a latency analysis to determine where potential bottlenecks may occur and then find a balance between desired performance and the cost of implementing the design. To achieve a desired performance level, you use PCI Express or HyperTransport to provide JPEG 2000 JPIP, 3D, AND TRANSCODING IMAGE COMPRESSION LIBRARIES · Powerful low-level C libraries · 64-bit & 32-bit, on multiple platforms · Optimized for multiple cores · Lossless and lossy mode · Compressed image optimization for JPIP · Compress to PSNR value or file size · Codestream and file format support · Control progression order, precinct sizes, and tile sizes DOWNLOAD A FULL-FEATURED TRIAL VERSION OF THE PICTOOLS SDK TODAY. Supported across: Microsoft® Windows® LINUX high-bandwidth, low-latency communication channels. Last, scour the literature for tricks that can accelerate computations—some tricks may actually be decades old but were impractical before the availability of multimegagate FPGAs. Consider different types of math for computations aside from basic integer and floating-point operations. Logarithmic computations or math based on residue number systems, for example, could execute faster than standard integer or floating-point-based code. In seismic processing software, wave migration algorithms often incorporate FFT as part of the solution. This algorithmic technique (the FFT approach) usually takes the following sequence: Apply the FFT, phase shift the data, and then apply the inverse FFT to obtain the next location of the traveling wave front. When this is computed on a processor via software, data is taken out of memory to compute the FFT, then the result is put back into memory. The resulting data is taken out of memory again to do the phase shift and the new result is put back into the memory. Lastly, the new result data is taken out so the inverse FFT can be computed and the final result is put back into memory. In such a linear execution, there are too many memory accesses that can slow down the execution. Using hardware to accelerate the algorithm, begin by taking the data out of memory and feeding it to a pipeline that executes the FFT and feeds the result into the phase shifter. The phase shifter then directly feeds its result into the inverse FFT. The output of the inverse FFT is then put back into memory. A typical application-level profile for a wave migration algorithm might look like: FFT Inverse FFT Phase Shift I/O Misc 35% 35% 25% 3% 2% Sun® Solaris IBM® AIX® Contact us for more information. W W W . P E G A S U S I M A G I N G . C O M Pegasus is a registered trademark of Pegasus Imaging Corporation in the United States. The names of actual companies and products mentioned herein may be the trademarks of their respective owners. Traditionally, these algorithms are executed using floating-point math operations because the input data is gathered from 24bit sensors and the output is often displayed as 24-bit color pixels. By implementing multiple floating-point units in an FPGA, the FPGA can outperform a CPU 5:1 on floatingpoint code, but can deliver a 10–100 time improvement on integer-based code. 38 Dr. Dobb’s Journal l www.ddj.com l June 2008 http://www.pegasusimaging.com http://www.pegasusimaging.com http://www.ddj.com

Table of Contents Feed for the Digital Edition of Dr. Dobb's Journal - June 2008

Dr. Dobb's Journal - June 2008 Contents Friday Night Fish Fry Alia Vox Developer Diaries There Must Be Contest Conversations Building a Test Harness for RTOS QT and Windows CE Software to Hardware Parallelization Performance Portable C++ Effective Concurrency The Agile Edge Swaine's Flames

Dr. Dobb's Journal - June 2008

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