Dr. Dobb's Journal - November 2007 - (Page 51)

d11jiri_p8db 9/11/07 12:55 PM Page 51 by Martin Soukup and Jiri Soukup State of the Art Reusable Associations An important feature that languages and tools ought to support Associations are a key concept in UML and Model-Driven Development (MDD), yet not supported by existing programming languages and their libraries. In this article, we describe a mechanism that implements reusable associations in C++, C#, or Java by adding two keywords, combined with a simple modification of the compiler. This interim solution is to use a code generator, which replaces the missing language features. The resulting library treats associations as first-class entities, treats associations, collections, and structural design patterns in the same uniform manner, and, with every compilation, automatically generates UML class diagrams. (Two similar libraries have been used commercially for over 10 years with excellent results.) The best way to explain this problem is with a realworld example. We chose the computer-aided design of silicon chips (VLSI circuits) because it involves complex data organization with only a few classes. A fully functional computer can be on a single chip, and the data to store and traverse are huge—millions of objects. Figure 1 explains the engineering concepts of building these chips. If you use standard class libraries, the initial code may look like Listing One, where ChipLib is a library storing both complete chips and partially designed blocks. ChipLib also keeps frequently needed basic geometries such as contacts. Associations among classes in Listing One are represented by collections, pointers, or by a combination of both—one relation may possibly require members in several classes. For example, the relation between Block and Terminal requires the two members shown in red. The problem with this code is that the associations are buried inside the class definitions; and when reading the code, the purpose of these members is obscured. Worse, in spite of the formal similarity to how associations are implemented, the green members in classes Master and Block do not belong to the same relation. Member Block::master points to the master of the block, not to the master in which the block is used. Martin is a Design Manager at Nortel. Jiri is a cofounder of Cadence Design Systems and president of Code Farms. You can contact them at jiri@codefarms.com Figure 1: A silicon chip is designed from blocks, which are hierarchically composed from smaller blocks and so on. This is a conceptual diagram, not a real circuit. Pins are points to which the outside signal nets may be attached. A set of pins connected together inside a block is a logical entity called “terminal” (shown as a dashed line). A terminal often has only one pin. The nets are formed by wires (rectangles assigned to one of the layers; here blue or red) and by contacts (geometries that connect several layers). The two parts of net1 are connected through one of the BLK blocks. November 2007 l www.ddj.com l Dr. Dobb’s Journal 51 http://www.ddj.com

Table of Contents Feed for the Digital Edition of Dr. Dobb's Journal - November 2007

Contents Hmmmm Alia Vox Developer Diaries Developer’s Notebook Smart Compilers - But Smart Enough? Conversations Grid-Enabling Resource-Intensive Applications Distributed Computing: Windows and Linux Adobe AIR: Desktop/Web Convergence Transparency on Demand Reusable Associations Effective Concurrency The Agile Edge Swaine’s Flames

Dr. Dobb's Journal - November 2007

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