EE Times - August 6, 2007 - (Page 27) Design www.eetimes.com Monday, August 6, 2007 Concepts, trends and analysis in systems design Tech Trends: Best of power management INSIDE under the hood Counterfeit parts, legitimate woes Analyzing dynamic voltage drop at 90 nm and beyond A design flow that assesses dynamic voltage drop early and accurately can save millions in mask and other nonrecurring engineering costs By Lihui Cao and Shashidhara S. Bapat p. 30 eetimes.com For a full version of the article to the left, “Analyzing dynamic voltage drop at 90 nm and beyond,” search article ID: 201201433 A s VLSI technology scales to 90 nanometers and beyond, ASIC vendors increasingly see power grid integrity issues in their designs and in the field, for two primary reasons. First, deep-submicron geometries require lower power supply voltages, which reduce the chip’s tolerance of noise (noise margin). Second, smaller geometries result in many more transistors per die. More transistors not only consume more power but also strain the chip’s internal power distribution network by causing dynamic voltage drop (DVD). A design flow that can analyze DVD early and accurately reduces the cost of chip debug and obviates respinning the chip for power at a later stage, potentially saving millions in mask and other nonrecurring engineering costs. TechOnline (techonline.com) Tap our education and design resources, ranging from Webinars and online courses to a library of white papers and how-to articles. View the latest products and evaluate your own in the VirtuaLab, as well as gain insight into your peers’ design approaches in Under the Hood, at www.techonline.com/ underthehood. Power noise, power integrity, dynamic (or instantaneous) voltage drop and other terms all refer to the issue of measurable decreases in supply voltage from the chip’s voltage supply pins to its internal areas. The supply voltage at the pins may be ideal, but line resistance, inductance effects and capacitive parasitics result in voltage drop, leading to delay and slew rate changes that ultimately cause setup and hold time violations. Setup violations will reduce chip speed; hold time violations can have more severe consequences and cause the chip to fail. Likewise, reduced noise margins make the chip more susceptible to glitches and increase the likelihood of failure. Decoupling capacitors (decaps) that reduce DVD can become a cause of Lihui Cao lower yield with oxide (Lihui.Cao@lsi. com) is a design breakdown. If not used engineer at LSI wisely, they also are a Logic Corp. He cause for increased leakhas a PhD in elecage power. trical engineering. The chip’s multiple modes of functional and Shashidhara S. test operations are also Bapat (Shashidcritical factors; designs will hara.S.Bapat@lsi. have a different current com) is a design consumption profile, reengineer at LSI Logic. He holds a sulting in different DVD bachelor’s degree hotspots per mode of operin telecommunications engineering. ation. The problem is particularly challenging be- cause it is dynamic: Voltage drop varies not only in space across the chip, traditionally known as IR drop, but also in time across the clock cycle as a function of the mode. What matters in computing dynamic voltage drop? Since DVD is a function of time-related factors such as operating frequency and mode, power integrity becomes a reliability issue: The designer may not see the problem in the lab if the chip’s operating conditions in the field are not adequately modeled and analyzed. The analysis must take into account operating frequencies, operating conditions and modes of operation that are expected to stress the power distribution network. For example, clock gating, a common technique to reduce power consumption, will cause huge spikes in L(di/dt) noise (the inductive component of DVD caused by instantaneous changes in current through the package) when the clock tree is “lit up.” Skew-balanced clock networks pose a similar strain. Likewise, many flip-flops toggle simultaneously in scan mode, straining the chip’s power network and causing DVD failures. Parasitic models should be comprehensive to encompass the power distribution network, including both on- and off-chip parasitics. Onchip parasitics should not only include the power grid itself but also the nonswitching capacitive effects of signal parasitics, decoupling capacitors and intrinsic cell capacitances. Off-chip parasitics should accurately model inductances and capacitances inherent in the physical structure of package, die and bonding wires. ■ August 6, 2007 | Electronic Engineering Times ■ about the authors >> Best-read DesignLine article for the most recent week: “Basics of ADCs and DACs, part 1,” www.dspdesignline.com, search article ID: 201002110 27 http://www.eetimes.com http://eetimes.com http://techonline.com http://www.techonline.com/underthehood http://www.dspdesignline.com http://www.dspdesignline.com
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