EETimes - Apollo - July 20, 2009 - 34

A p o ll o El ec t r o nic s Figure 4: ULD dual-diode AND gate Systems Division (FSD) who worked on the packaging for the ULD. Munroe recalled that “the resistors on the bottom were actively trimmed with sand or air abrasion, and the first ones we built went to the Hudson River Valley” for use in IBM’s commercial compute systems. Naturally, the dice use bipolar technology, since at the time of 34 EE Times | Apollo | July 20, 2009 manufacture MOS was still a ways off. Instead of TTL, however, the module uses diode-transistor logic. Electrical probing reveals that six of the seven dice are dual diodes with a common anode; the seventh is an NPN transistor. Munroe offered some intriguing trivia on the bipolar devices’ production, stating that they “consisted of a pure silicon layer over the active areas which was transformed to pure silica using hot steam.” Figure 4 is an optical photograph of one of the dual-diode chips. The two squares in the center of the die appear to be mask alignment marks for the P and N diffusions. The dual diodes function as a two-input AND gate when the common anode is collected to VCC through a suitable pullup resistor. Figure 5 is the electrical schematic of the arrangement. Figure 6 shows the layout of the lateral NPN bipolar transistor. The semiconductor technology, not surprisingly, is single-metal diffusion. Moore’s Law was in its infancy, and the smallest features are the base and emitter contact windows, both about 30 microns wide. Munroe, who continued his career in electronics packaging at Motorola after 30 years with IBM, provided additional details on the chip-join construction. “The balls were nickelplated copper that were tin coated and attached by solder” to the package-level metallization, he said. “The technology formed the basis for what became the circuit modules for the larger ceramic packages of the System/360 [mainframe].” Those who have followed IBM’s development and application of flipchip technology appreciate the significance of these early efforts. Said Munroe: “It was our early investigation into solder properties for SMT that led us to be leaders in the fa- Figure 5: Two-input DTL AND gate schematic

EETimes - Apollo - July 20, 2009

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