Embedded Systems Design Europe - February 2008 - (Page 22)

feature stants, formulas, processes, and procedures that are used by multiple modules or submodules within their design, he or she can create a custom package. By doing this, the functions in the userdeﬁned package can be shared with other designers and projects. A userdeﬁned library/package is an easy way to repeatedly use speciﬁc HDL elements in multiple ﬁles with the luxury of only deﬁning its elements once. Assuming a designer creates a package called my_package and stores this package in the library called Test, the following command would make the package visible, thereby allowing its contents to be used in the source ﬁle. LIBRARY Test; USE Test.my_package.ALL; User/designer-deﬁned packages are similar to those supplies by vendors, such as Xilinx, whose packages contain elements such as RAMs, counters, and buffers. Xilinx’s “vcomponents” package contains constants, attributes, types, and components that become available once the library and package are visible to the design. The package contains components like AND3, which is a three-input AND gate, and NAND3, a three-input NAND gate. The “vcomponent” package provides timing information, the I/O port names (used to instantiate components in design), and other information used by synthesis and simulation tools. The vendor’s package becomes visible in the same manner as the standard and userdeﬁned libraries. To use the elements in Xilinx’s “vcomponent” package, designers must make the library visible. For example, the following command makes the “Xilinx” library with vcomponent package visible to the design: LIBRARY Xilinx; USE Xilinx.vcomponents.ALL; diately follows the library declaration. Each entity has an assigned name; Monitor is the entity name of the VHLD code in Listing 1. Just as the library declaration section makes libraries and packages visible to the design, the entity section makes the I/Os visible to other source ﬁles and the design and can represent the I/Os as physical FPGA pins. VHDL designs can contain one source ﬁle or a hierarchy of multiple ﬁles. Hierarchical ﬁle structures consist of several ﬁles connected through the signals declared in their entities. Figure 2 shows a simpliﬁed hierarchical ﬁle structure for a home security system. On the other hand, if the design is only one ﬁle, the top-level entity declaration deﬁnes all of the I/O that represents physical FPGA pins. All I/O signals deﬁned in this section must have unique names, indicated signal direction (input or output), and number of bits reserved for the signal. From Listing 1, reset is an input, only one data-bit wide and is a std_logic data type. The keyword END followed by the entity’s name signiﬁes the end of the entity. All entities must be associated with an architecture section. Architecture section The architecture section, which contains the circuit description, is the body of the VHDL source code. The libraries, packages, and signals work together to develop the desired functions. Like the entity, each architecture must have an assigned name. The format for declaring the architecture is the reserved word Architecture followed by its name Door_monitor, then the reserved word Of, then the entity’s name Monitor. Signals not deﬁned in the entity section are deﬁned in this section. The signal assignment format consists of the reserved word Signal followed by the signal name and then the data type (such as std_logic and std_logic_vector), as in Listing 1. Like names deﬁned in the entity, each signal name must be unique and have a data type. This section is also for declaring constants, variables, and other data types. Signals can be thought of as wires used to connect functions and store values. After deﬁning all the design’s signals, the designer is ready to develop the code that describes the desired functions. The reserved word Begin signiﬁes the start of the next subsection, which combines the concurrent and sequential statements. Concurrent statements update or change value at anytime. The signal assignment immediately following the ﬁrst reserved word BEGIN in Listing 1 is an example of a concurrent statement. Sequential statements update or change value when signals in the sensitivity list (see Listing 1) change state. Signals in “processes” are sequential statements. Most processes have a sensitivity list, process name, and circuit description (HDL code) between reserve words BEGIN and END PROCESS. The process name precedes the reserved word Process, and the sensitivity list is enclosed in the parenthesis. Listing 1 contains two processes. The ﬁrst is checking_door_status, which has a sensitivity list that contains three signals: reset, clock_20mhz, and reset_ start_timer. The second process is set_alarm_enable, which only has two signals, reset and clock_ 20mhz, in its sensitivity list. Signals in a process that update or change following a clock edge are called synchronous signals. Start_500ns_timer in the checking_door_status process is an example of a synchronous signal. The architecture section closes by using the reserved word END followed by the architecture’s name. SIMULATE OR SYNTHESIZE One or more designers may be responsible for a design. A number of factors inﬂuence the numbers designers needed, such as design complexity and size; the designers’ skill level; and the designers’ schedule and availability. Regardless of the number of designers, after the design is completed, there are a couple of options. He or she may choose to simulate or synthesize the Once all the libraries and packages are visible, this section is complete. Entity declaration The entity declaration section imme22 JANUARY – FEBRUARY 2008 | embedded systems design europe | www.embedded.com/europe 018-019-020-021-022-023-024-025-22 22 7/02/08 11:28:01 http://www.embedded.com/europe

Table of Contents Feed for the Digital Edition of Embedded Systems Design Europe - February 2008

Embedded Systems Design Europe - February 2008 Contents ARTEMIS and ENIAC Get Parlimentary Approval Product Teardown Videos Come On Screen Esterel and Abslnt Integrate Products Microsoft Opens Windows to Networked Embedded Applications Trango Embeds Virtualization Tool in Cavium's Multicore CPUs MindTree - ADI Develop Security DVR Platform NXP Extends Deal with ARM to Cover MCUs Automotive and Embedded to Dominate DATE 08 ZigBee Spec Gets Smart On Energy Updated Card Spec Provides for Power-On Boot The Basics of Embedded Multitasking On a PIC Cover Feature: The Art of FPGA Construction Is Symmetric Multiprocessing For You? Accelerating MATLAB Using MEX-Files ARM Provides the Microcontroller Solution Embedded World Advertising Contracts

Embedded Systems Design Europe - February 2008

For optimal viewing of this digital publication, please enable JavaScript and then refresh the page. If you would like to try to load the digital publication without using Flash Player detection, please click here.