Embedded Systems Design Europe - February 2008 - (Page 23)

feature VHDL language rules apply. Each tester has a style in which he or she writes a testbench, which can be automatic or manual and can use external ﬁles for simulation and analysis. Automatic testbenches can analyze simulation data and provide a ﬁnal result, output error data, or other important information. Manual testbenches require the tester to manually analyze the data. An example of an automatic testbench would be one that reads valid data from an external ﬁle, compares it with simulation data, and writes the ﬁnal pass/fail results to an external ﬁle. External ﬁles are useful for duplicating events seen on actual hardware. Data can be taken from the hardware, stored in an external ﬁle, then read into a testbench and used as the input stimulus. Many simulators accept both waveform and testbenches as input stimulus; consult your simulator user’s manual for acceptable formats. Some popular simulators are Mentor Graphics’ ModelSim, Aldec’s Riviera, and Altera’s Quantus II. There are three levels of simulation: register transfer level (RTL), functional, and gate level. Each occurs at a speciﬁc place in the development process. RTL follows the design stage; functional follows synthesis and after implementation is completed the gate level simulation. Generally, the stimulus developed for the RTL simulation is reusable without modiﬁcation for each level of simulation. SIMULATION The initial simulation performed immediately after the design stage is the RTL simulation. This involves directly applying the stimulus to the design. RTL simulation only lets designers verify that the logic is correct. No realistic timing information is available to the simulator. Therefore, no serious timing exists for the design. The only timing information that can be available to the simulator is tester generated. Much like input stimulus, a tester can insert simulated or injected delays into the original HDL design, as in Listing 1. Most synthesis tools (discussed later) will ignore 23 design. There isn’t a hard and fast rule stating you must simulate before synthesis. There are advantages to each option, and designers must determine which step is most beneﬁcial. In fact, there may be times when a designer decided to simulate following the completion of the initial design while another time decide to synthesize. Each option lets the designer detect and correct different types of errors. Simulating the design prior to synthesis allows logic errors and design ﬂaws to be resolved early in the development process. Synthesizing lets the designer resolve synthesis errors prior to logic errors and design ﬂaws. Ideally, the designer would perform minimal simulation, leaving the more stringent testing to a code tester. The original code designer shouldn’t test his own code because he’s less likely to detect speciﬁc design ﬂaws such as: 1. Misinterpretation of requirements; if the designer misunderstood a requirement, he or she will test and evaluate the design based on that misunderstanding. 2. It’s more difficult for a person to find his own errors. A third-party generally tests the code more rigorously and is more eager to find bugs than the original designer. Regardless of who performs the simulations, the process is the same. For the sake of this article, we’re going to assume the testing is performed by a code tester, not the original designer. Simulation is the act of verifying the HDL or graphical digital designs prior to actual hardware validation. The circuit’s input-signal characteristics are described in HDL or in graphical terms that are then applied to the design. This lets the code tester observe the outputs’ behavior. It may be necessary to modify the source code during simulation to resolve any discrepancies, bugs, or errors. Simulation inputs or stimulus are inputs that mimic realistic circuit I/Os. Stimulus forces the circuit to operate under various conditions and states. The greatest beneﬁt of stimulus is the ability to apply a wide range of both valid and invalid input-signal characteristics, test circuit limits, vary signal parameters (such as pulse width and frequency), and observe output behavior without damaging hardware. Stimulus can be applied to the design in either HDL or graphical/waveform format. Generally, when a tester or designer speaks of a testbench, he’s referring to applying stimulus to the design in the form of HDL. Listing 2 shows an example of a VHDL stimulus or testbench ﬁle. The testbench looks similar to the actual VHDL design. Hence, the same www.embedded.com/europe | embedded systems design europe | JANUARY – FEBRUARY 2008 018-019-020-021-022-023-024-025-23 23 7/02/08 11:28:19 http://www.embedded.com/europe

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Embedded Systems Design Europe - February 2008 Contents ARTEMIS and ENIAC Get Parlimentary Approval Product Teardown Videos Come On Screen Esterel and Abslnt Integrate Products Microsoft Opens Windows to Networked Embedded Applications Trango Embeds Virtualization Tool in Cavium's Multicore CPUs MindTree - ADI Develop Security DVR Platform NXP Extends Deal with ARM to Cover MCUs Automotive and Embedded to Dominate DATE 08 ZigBee Spec Gets Smart On Energy Updated Card Spec Provides for Power-On Boot The Basics of Embedded Multitasking On a PIC Cover Feature: The Art of FPGA Construction Is Symmetric Multiprocessing For You? Accelerating MATLAB Using MEX-Files ARM Provides the Microcontroller Solution Embedded World Advertising Contracts

Embedded Systems Design Europe - February 2008

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