Embedded Systems Design Europe - February 2008 - (Page 25)

feature tion level offers various beneﬁts. RTL uncovers logic errors, the functional level veriﬁes that the pre- and post-synthesis designs are equivalent, and the gate level uncovers timing errors. Some beneﬁts to spending sufﬁcient time generating quality testbenches and simulation are reduced time troubleshooting hardware (generally, cheaper to testbench troubleshoot than hardware troubleshoot) and a decrease in the chance of damaging hardware resulting in a faster time to market. Opting to omit simulation and testbenching will generally cost the project additional time and money. Lab testing requires collecting and setting up test equipment (such as a logic analyzer and oscilloscope) and depending on the equipment used, the designer may have a limited number of signals available. Or, the desired signal must be made available on an output, which requires additional time. Simulation is valuable and as a guideline, at least 2X the number of hours spent writing the code should be spent developing and testing the code. DESIGN SYNTHESIS While some designers prefer to proceed directly to simulation, I prefer to synthesize the design. Synthesis is the process that reduces and optimizes the HDL or graphical design logic. Some third-party synthesis tools are available as a part of the FPGA vendor’s complete development package. Synplicity’s Synplify and Mentor Graphics’ Leon- ardoSpectrum, Precision RTL, and Precision Physical are examples of third-party synthesis tools. Xilinx offers ISE Project Foundation, which is a complete development application that includes a synthesis tool. Altera has Quartus II Integrated Synthesis, QIS. Although some FPGA vendors offer synthesis, they still recommend using a third-party’s synthesis tools. The synthesis tool must be set up prior to actually synthesizing the design. Synplicity’s Synplify goes through a common set-up process, as it involves providing the design ﬁles (completed during design stage) and information about the FPGA. FPGA information includes the vendor’s name, the speciﬁc part or family, the package type, and the speed. The synthesis process takes this information and the user-deﬁned constraints and produces the output netlist. A constraints ﬁle speciﬁes information like the critical signal paths and clock speeds. After completing set-up, synthesis can begin. General synthesis ﬂow for tools like Synplicity’s Synplify involves three steps, creating structural element, optimizing, and mapping. Figure 3 shows a synthesis ﬂow diagram. The ﬁrst step in the synthesis process is to take the HDL design and compile it into structural elements. This means that the HDL design is technology independent. Synplify graphically represents this step as the “RTL Schematic View”, viewable in Synplify. The next step involves optimizing the design, making it smaller and faster by removing unnecessary logic and allowing signals to arrive at the inputs or output faster. The goal of the optimizing process is the make the design perform better without changing the circuit’s functions. The ﬁnal step in the synthesis process involves mapping or associating the design to the vendor speciﬁc archi- 018-019-020-021-022-023-024-025-25 25 7/02/08 11:28:43 http://www.syslogic.com http://www.syslogic.com

Table of Contents Feed for the Digital Edition of Embedded Systems Design Europe - February 2008

Embedded Systems Design Europe - February 2008 Contents ARTEMIS and ENIAC Get Parlimentary Approval Product Teardown Videos Come On Screen Esterel and Abslnt Integrate Products Microsoft Opens Windows to Networked Embedded Applications Trango Embeds Virtualization Tool in Cavium's Multicore CPUs MindTree - ADI Develop Security DVR Platform NXP Extends Deal with ARM to Cover MCUs Automotive and Embedded to Dominate DATE 08 ZigBee Spec Gets Smart On Energy Updated Card Spec Provides for Power-On Boot The Basics of Embedded Multitasking On a PIC Cover Feature: The Art of FPGA Construction Is Symmetric Multiprocessing For You? Accelerating MATLAB Using MEX-Files ARM Provides the Microcontroller Solution Embedded World Advertising Contracts

Embedded Systems Design Europe - February 2008

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