Embedded Systems Design Europe - February 2008 - (Page 26)

feature tecture. The mapping process takes the design and maps or connects it using the architecture of the speciﬁc vendor. This means that the design connects to vendor-speciﬁc components such as look-up tables and registers. The optimized netlist is the output of the synthesis process. This netlist may be produced in one of several formats. Edif is a general netlist format accepted by most implementation tools, while .xnf format is speciﬁc to Xilinx and is only recognized by Xilinx’s implementation. In addition to the optimized netlist, many synthesis tools like Synplify will produce a netlist for gate-level simulation and other report ﬁles. Stimulus applied to this netlist instead of the original HDL design produces the functional-level simulation, which lets the designer verify that the synthesis process hasn’t changed the design’s functions. At this point, synthesis is complete and ready for the implementation process. Each FPGA vendor has its own implementation tool, such as Xilinx’s Project Navigator and Altera’s Quartus II’s. DESIGN IMPLEMENTATION The ﬁnal stage in the FPGA development process is the design implementation, also known as place and route (PAR). If the FPGA vendor has a complete development tool, meaning it can perform synthesis, and the design is synthesized using this tool, little or no set-up is required for PAR. However, if a third-party synthesis tool is used, the implementation tool must be set up, which involves directing the PAR tool to the synthesized netlist and possibly a constraint ﬁle. The constraint ﬁle contains information such as maximum or minimum timing delays for selected signal(s) and I/O pin assignments. Pin assignments can be automatic (performed by the tool) or manual (dictated by the designer). Automatic pin assignment is generally the best option for new designs, as it lets the 26 tool more effectively route the design without having ﬁxed pin assignments. It may be necessary to manually assign signals to speciﬁc pins to achieve easy board routing, to provide the minimum signal route for timing-critical signals, or be compatible with legacy designs. There are numerous reasons why manual pin assignments would be necessary. But regardless of the reason, the designer must make this information available to the PAR tool, which is done by creating a user constraint ﬁle that’s used by the PAR tool. After completing setup, the PAR process can begin. Each PAR tool may have a slightly different approach to design implementation, so consult your PAR documentation. Xilinx’s Foundation or Project Navigator performs design implementation in three steps, translate, ﬁt, and generate programming ﬁle. INCONSISTENCIES Step one, called translate, involves verifying that the synthesized netlist is consistent with the selected FPGA architecture and there are no inconsistencies in the constraint ﬁle. Inconsistencies would consist of assigning two different signals to the same pin, assigning a pin to a power or ground pin, or trying to assign a non-existing design signal to a pin. If the design fails either check, the translate step will fail and the implementation process will be stopped. Translate errors must be corrected and the translation step must be error free before advancing to step two, which is the ﬁt stage. This step involves taking the constraints ﬁle and netlist and distributing the design logic in the selected FPGA. If the design is too large or requires more resources or available logic than the selected device offers, the ﬁtter will fail and halt the implementation process. To correct this type of error, replace the current FPGA with a larger one and re-synthesize, and repeat PAR for the design. A successful ﬁt stage is necessary to proceed to generate the programming ﬁle stage. All timing information is available and many PAR tools will provide the required ﬁles necessary for the simulator to perform a timing simulation. The ﬁnal step is to generate the programming ﬁle, which can be stored in ﬂash memory, PROMs, or directly programming into the FPGA. JTAG and third-party programmers like Data I/O are two programming methods used to store the programming ﬁle in memory. The appropriate format depends on the FPGA vendor, the programming method, and the device used to hold the programming. There are various output formats; consult your documentation for the correct one. In addition to the implementation process creating the programming ﬁle, there are several output report ﬁles created, such as a pad ﬁle. The pad ﬁle contains information such as signal pin assignment, part number, and part speed. BEYOND THE BASICS This article gives some basic examples of the FPGA development process, so a new embedded systems designer, manager, technical lead from other disciplines, or someone wanting to diversify his or her skills can understand what it takes to develop and implement a digital design in a FPGA. The generic process provided here will vary depending on the FPGA tools since each vendor may perform some of these tasks in a slight different manner. A good resource for furthering your knowledge is Essential VHDL RTL Synthesis Done Right (Sundar Rajan, F.E. Compton Co, 1998). Gina R. Smith (Gina_R_Smith@BrownSmithRDL.com) is CEO and owner of Brown-Smith Research and Development Laboratory Inc., an engineering services, technical training and consulting company. She is also a senior systems engineer, with responsibility for performing failure mode effect and criticality analysis, requirements analysis and deﬁnition, creating physical and functional block diagrams, and evaluating design tool needs. JANUARY – FEBRUARY 2008 | embedded systems design europe | www.embedded.com/europe 018-019-020-021-022-023-024-025-26 26 7/02/08 11:28:58 http://www.embedded.com/europe

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Embedded Systems Design Europe - February 2008 Contents ARTEMIS and ENIAC Get Parlimentary Approval Product Teardown Videos Come On Screen Esterel and Abslnt Integrate Products Microsoft Opens Windows to Networked Embedded Applications Trango Embeds Virtualization Tool in Cavium's Multicore CPUs MindTree - ADI Develop Security DVR Platform NXP Extends Deal with ARM to Cover MCUs Automotive and Embedded to Dominate DATE 08 ZigBee Spec Gets Smart On Energy Updated Card Spec Provides for Power-On Boot The Basics of Embedded Multitasking On a PIC Cover Feature: The Art of FPGA Construction Is Symmetric Multiprocessing For You? Accelerating MATLAB Using MEX-Files ARM Provides the Microcontroller Solution Embedded World Advertising Contracts

Embedded Systems Design Europe - February 2008

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