Embedded Systems Design Europe - March 2008 - (Page 36)

multicore Multicore processors are here to stay but memory is a bottleneck. Is multicore hype or reality? BY JACK G. GANSSLE F or many years, processors and memory evolved more or less in lockstep. Early CPUs like the Z80 required a number of machine cycles to execute even a NOP instruction. At the few-megahertz clock rates then common, processor speeds nicely matched EPROM and SRAM cycle times. But for a time, memory speeds increased faster than CPU clock rates. The 8088/6 had a prefetcher to better balance fast memory to a slow processor. A very small (4 to 6 bytes) FIFO isolated the core from a bus interface unit (BIU). The BIU was free to prefetch the mostlikely-needed next instruction if the core was busy doing something that didn’t need bus activity. The BIU thus helped maintain a reasonable match between CPU and memory speeds. Even by the late 1980s, processors were pretty well matched to memory. The 386, which (with the exception of ﬂoating-point instructions) has a programmer’s model very much like Intel’s latest highend offerings, came out at 16 MHz. The three-cycle NOP instruction thus consumed 188 nsec, which partnered well with most zero wait-state memory devices. But clock rates continued to increase while memory speeds started to stagnate. The 386 went to 40 MHz, and the 486 to over 100. Some of the philosophies of the reduced instruction set (RISC) movement, particularly single-clock instruction execution, were adopted by CISC vendors, further exacerbating the mismatch. Vendors turned to Moore’s Law as it became easier to add lots of transistors to processors to tame the memory bottleneck. Pipelines sucked more instructions onchip, and extra logic executed parts of many instructions in parallel. A single-clock 100 MHz processor consumes a word from memory every 10 nsec, but even today that’s pretty speedy for RAM and impossible for ﬂash. So onchip cache appeared, again exploiting cheap integrated transistors. That, plus ﬂoat- 36 MARCH 2008 | embedded systems design europe | www.embedded.com/europe 036-037-038_ESDE.indd 36 5/03/08 17:31:04 http://www.embedded.com/europe

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Embedded Systems Design Europe - March 2008 Distributors to Increase Embedded Focus Kontron and Quanta to Join Forces Coverity Raises $22m as European Business Booms Help is at Hand for Europe's Industrial Control Developers Milestones in Embedded Systems Microsoft is Recruiting for Embedded Center in Aachen European Designers to Win Cash for Green Designs Duo Work on Smaller Form Factor Europe Invests in Real-Time Java for Multicore Systems Curtiss-Wright Buys Pentland Systems Designing DSP-Based Motor Control Using Fuzzy Logic Lower the Cost of Intelligent Power Control with FPGAs Virtualizing Embedded Linux Back to the Future: Manchester Encoding Is Multicore Hype or Reality New Products Advertising Contacts

Embedded Systems Design Europe - March 2008

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