Embedded Systems Design Europe - March 2008 - (Page 37)

multicore ing point and a few other nifty features meant the 486’s transistor budget was over four times as large as the 386. Pentium-class processors took speeds to unparalleled extremes, before long hitting two and three gigahertz. Memory devices at 0.33 nsec are impractical for a variety of reasons, not the least of which is the intractable problem of propagating those signals between chip packages. Few users would be content with a 3-GHz processor stalled by issuing 50 wait states for each memory read or write, so cache sizes increased more. But even on-chip, zero wait-state memory is expensive. Caches multiplied, with a small, fast L1 backed up by a slower L2 and in some cases even an L3. Yet more transistors implemented immensely complicated speculative branching algorithms, cache snooping and more, all in the interest of managing the cache and reducing inherently slow bus trafﬁc. And that’s the situation today. Memory is much slower than processors and has been an essential bottleneck for ﬁfteen years. Recently CPU speeds have stalled as well, limited now by power dissipation problems. As transistors switch, small inefﬁciencies convert a tiny bit of V to heat. And even an idle transistor leaks microscopic amounts of current. Small losses multiplied by hundreds of millions of devices means very hot parts. Ironically, vast numbers of the transistors on a modern processor do nothing most of the time. No more than a single line of the cache is active at any time, most of the logic to handle hundreds of different instructions stands idle till infrequently needed, and page translation units that manage gigabytes handle a single word at a time. But those idle transistors do convert the power supply to waste heat. The “transistors are free” mantra is now stymied by power concerns. So limited memory speeds helped spawn hugely complex CPUs, but the resultant heat has curbed clock rates, formerly the biggest factor that gave us faster computers every year. CC In the supercomputing world, similar dynamics were at work. Gallium arsenide logic and other exotic components drove clock rates high, and liquid cooling kept machines from burning up. But long ago, researchers recognized the futility of making much additional progress by spinning the clock-rate wheel ever higher and started building vastly parallel machines. Most today employ thousands of identical processing nodes, often based on processors used in standard desktop computers. Amazing performance comes from massively parallelizing both the problems and the hardware. To continue performance gains, desktop CPU vendors co-opted the supercomputer model and today offer a number of astonishing multicore devices, which are just two or more standard processors assembled on a single die. A typical conﬁguration has two CPUs, each with their own L1 cache. Both share a single L2, which connects to the outside world via a single bus. Embedded versions of these parts are available as well and share much with their desktop cousins. Symmetric multiprocessing (SMP) has been deﬁned in a number of different ways. I chose to call a design using multiple identical processors that share a memory bus an SMP system. Thus, multicore offerings from Intel, AMD, and some others are SMP devices. SMP will yield performance improvements only (at best) insofar as a problem can be parallelized. Santa’s work cannot be parallelized (unless he gives each elf a sleigh), but delivering mail-order products keeps a ﬂeet of UPS trucks busy and efﬁcient. Amdahl’s Law gives a sense of the beneﬁt accrued from using multiple processors. In one form, it gives the maximum speedup as: where f is the part of the computation that can’t be parallelized, and n is the number of processors. With an inﬁnite number of cores, assuming no other mitigating circumstances, Figure 1 shows (on the vertical axis) the possible speedup versus (on the horizontal axis) the percentage of the problem that can’t be parallelized. The Law is hardly engraved in stone as there are classes of problems called “embarrassingly parallel” where huge numbers of calculations can take place simultaneously. Supercomputers have long found their niche in this domain, which includes problems like weather www.embedded.com/europe | embedded systems design europe | MARCH 2008 37 036-037-038_ESDE.indd 37 5/03/08 17:31:20 http://www.embedded.com/europe

Table of Contents Feed for the Digital Edition of Embedded Systems Design Europe - March 2008

Embedded Systems Design Europe - March 2008 Distributors to Increase Embedded Focus Kontron and Quanta to Join Forces Coverity Raises $22m as European Business Booms Help is at Hand for Europe's Industrial Control Developers Milestones in Embedded Systems Microsoft is Recruiting for Embedded Center in Aachen European Designers to Win Cash for Green Designs Duo Work on Smaller Form Factor Europe Invests in Real-Time Java for Multicore Systems Curtiss-Wright Buys Pentland Systems Designing DSP-Based Motor Control Using Fuzzy Logic Lower the Cost of Intelligent Power Control with FPGAs Virtualizing Embedded Linux Back to the Future: Manchester Encoding Is Multicore Hype or Reality New Products Advertising Contacts

Embedded Systems Design Europe - March 2008

For optimal viewing of this digital publication, please enable JavaScript and then refresh the page. If you would like to try to load the digital publication without using Flash Player detection, please click here.