Embedded Systems Design Europe - April 2008 - (Page 14)

news MIPs adds multi-core option to portfolio While some other embedded IP offerings have already made the move to multi-core, MIPS Technologies’ says the performance advantage inherent in its single core processors made it unnecessary for it to do so until now. Previously its has optimized single core performance by maximizing single pipeline efﬁciency via multi-threading in the MIPS32 34K core, and increasing processor headroom and 1GHz+ frequencies with a superscalar, out-oforder pipeline in its MIPS32 74K core. Now that it has maximized performance on a single core, the company believes it’s time to move to a multi-core implementation. As performance demands increase in certain applications – for example set-top boxes or residential gateways – traditional frequency scaling can’t fully answer the challenge. The deep pipeline can only go so deep before power and memory limitations make it prohibitive. So MIPS Technologies recently introduced the MIPS32 1004K coherent processing system – a multi-threaded, multiprocessor licensable IP core. It provides up to four single- or multithreaded processors integrated with advanced system coherency. Designers can add CPUs to scale performance to their application requirements. The multi-core coherence manager (CM), the foundation block for system coherency, is conﬁgurable for one to four single- or multi-threaded cores. Other options include a global interrupt controller (GIC), which provides support for both system and inter-processor interrupts, and a sepa14 rately available L2 cache controller. Users can conﬁgure the number of virtual processing elements (VPEs) and TLB/cache/RAM sizes, choose to leverage multi-threading and ﬂoating point units (FPUs), and add custom instructions, coherence-aware on-chip debug/ trace instrumentation, and probes and software tools. An I/O coherence unit (IOCU) provides optional hardware support for IO peripherals. Maintaining I/O coherency can signiﬁcantly impact CPU performance for many performance-oriented applications that have high I/O data movement requirements. The 1004K features both a hardware block and software features to gain back CPU performance previously used for this purpose. The 1004K core provides a highly scalable performance migration path for the MIPS32 24K and 34K core families. Since the 1004K core is MIPS32compliant, designers can leverage an extensive base of existing software. The 1004K base core has a 9stage pipeline delivering more than 1.5 DMIPS/MHz per core, supports single- or dual-threaded operation per core, uses Virtual Processing Elements (VPEs) for hardware multi-threading, provides integer (1004Kc) and ﬂoating point (1004Kf) versions and support for Revision 1 of MIPS32 DSP ASE. A coherency port has duplicate data cache tags for background coherency checks. Design-time conﬁgurability provides inclusion and sizing of instruction and data TLBs, caches, scratchpad RAM and other options. The coherency management unit manages coherency using the MESI protocol, it operates at the same clock (1:1) as CPUs for maximum performance, provides a 256-bit extended interface for maximum throughput to (optional) L2 cache controller and supports performance enhancements via L1 cache-to-cache transfers, speculative reads to external memory, and globalized cache operations. Global conﬁguration registers are provided for conﬁguring/controlling CM scheme. The I/O coherence unit can be used to bridge non-coherent I/O peripheral transfer and makes transactions coherent and supports per transaction attributes for snooping L1 caches, L1+L2 caches, or non-coherent transactions, plus I/O prioritization. The global interrupt controller can be used(GIC) to supports system-level interrupts; inter-processor interrupts, to route interrupts to particular core or VPE and conﬁgurable up to 256 system interrupts. Development tools available for use with the 1004K include the MIPS SDE, a GNU based toolchain optimized to support MIPS cores; MIPSsim, a bus functional modeling and instruction set simulator and System Navigator probe, a EJTAG and PDtrace probe. APRIL 2008 | embedded systems design europe | www.embedded.com/europe 014_ESDE.indd 14 9/04/08 17:23:32 http://www.embedded.com/europe

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Embedded Systems Design Europe - April 2008 Contents Chip Industry Confronts 'Software' Gap Wind River's VxWorks OS Part of the nEUROn UCAV Demonstrator iSuppli Cuts Electronic Equipment Forecast Study Says GigE Vision Not Mature Chip Aids Wireless Health Monitoring Kontron Reports Strong Financial Growth Xilinx Completes Virtex-5 Line-Up French Project Builds Open Platform Home Automation Group Uses Enocean Radio Layer MIPs Adds Multi-Core Option to Portfolio Cover Feature: Next Gen Programmable Chips: Why Can't Hardware Be More Like Software? Improving Productivity & Quality With Domain-Specific Modeling Efficient CRC Calculation With Minimal Memory Footprint Do-It-Yourself Linux Embedded Development Tools Hardware/Software Verification Enters the Atomic Age New Products Advertising Contacts

Embedded Systems Design Europe - April 2008

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