Embedded Systems Design Europe - April 2008 - (Page 18)

cover feature the target of a software program is a well-understood and well-constrained machine, the process of translating the design intent (source code) into the device instructions (object code) is reasonably straightforward and well understood. Another very interesting side effect of the differences between HDL processing and software compilation is that the HDL must pass through synthesis, ﬁtting, placement, and routing before a target is formed. Each of these steps is quite long compared with compilation, and myriad equivalent results can emerge, the selection depending on any number of random variables or events. Contrast this with software compilation that is typically a single-pass process that’s extremely efﬁcient in terms of computing resources and time. (Figure 3) An interesting thought exercise is to consider how changes in a module can affect the rest of the design. The changes are especially important to understand because custom silicon is all about incremental (and often lastminute) modiﬁcations to merge reality with the marketing speciﬁcation. An HDL-based design that targets a sea-of-gates (FPGA, gate-array, ASIC) will be forced to make tradeoffs between device resources based on the changes in the design. Even if a module is fully isolated in terms of synthesis to a netlist, the placement and routing process will commence a series of tradeoffs that will affect the balance of the otherwise untouched design. The result is the well-known challenge of timing closure after minor design changes. Now consider the programmable device that is based on a processor. Code modules are generally selfcontained and well-behaved in terms of changes and impacts on the rest of the design. For example, changes in a code module cannot affect other code modules in terms of silicon utilization – that is because the essential nature of a processor is that the gates are intended for reuse by all of the opcodes. There are no tradeoffs per se; the entire design phase of “ﬁtting or place & route” is replaced by the temporal time-slicing nature of a processor and a program counter, making a design based on a software-ﬂow and a processor architecture more resilient to changes in the design. It seems to be a universal rule that there will be changes, there will be unexpected results, and marketing will require changes mere moments before a product has to ship. These factors favor a software-based approach. VERIFYING HARDWARE DESIGN Once the target netlist or object ﬁle is created, it’s usually simulated with an appropriate set of stimuli and expected results so that an automation tool can “probe” the design to verify functionality. In addition to simulating and debugging, it’s standard practice to evaluate the design by putting it into 18 APRIL 2008 | embedded systems design europe | www.embedded.com/europe 015-016-017-018-019_ESDE.indd 18 9/04/08 13:19:22 http://www.embedded.com/europe

Table of Contents Feed for the Digital Edition of Embedded Systems Design Europe - April 2008

Embedded Systems Design Europe - April 2008 Contents Chip Industry Confronts 'Software' Gap Wind River's VxWorks OS Part of the nEUROn UCAV Demonstrator iSuppli Cuts Electronic Equipment Forecast Study Says GigE Vision Not Mature Chip Aids Wireless Health Monitoring Kontron Reports Strong Financial Growth Xilinx Completes Virtex-5 Line-Up French Project Builds Open Platform Home Automation Group Uses Enocean Radio Layer MIPs Adds Multi-Core Option to Portfolio Cover Feature: Next Gen Programmable Chips: Why Can't Hardware Be More Like Software? Improving Productivity & Quality With Domain-Specific Modeling Efficient CRC Calculation With Minimal Memory Footprint Do-It-Yourself Linux Embedded Development Tools Hardware/Software Verification Enters the Atomic Age New Products Advertising Contacts

Embedded Systems Design Europe - April 2008

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