Embedded Systems Design Europe - April 2008 - (Page 19)

cover feature software compilers are inherently more stable and reliable than an HDL ﬂow. This is no comment on the engineers who develop the EDA tools; they are some of the very best software authors and architects – it’s just that they’re pushing a much bigger rock up a much bigger hill. LEARNING NEW TRICKS Moving to a world where systems are constructed using software images running on vanilla silicon is feasible and should help speed up development cycles, reduce development costs, and improve the ﬂexibility and maintainability of designs. So, a software approach to system design is desirable on a number of levels. For some time, there have been efforts to adapt programming languages for use as hardware description languages, the “C to gates” ﬂows. Many designs originate as C-based descriptions for basic evaluation, so it’s natural to want to migrate that model into the actual silicon through an automated process. The problem is that programming languages like C do not contemplate events or timing in a way that’s meaningful to integrated circuitry with its inherent parallelism. It’s a case of trying to use a well-bounded tool for an ill-suited job Simply using a software-based ﬂow is not sufﬁcient to provide the efﬁciency and ﬂexibility demanded by the engineers building electronic systems. It’s also necessary to give the engineers an efﬁcient instruction base and the correct silicon architecture. Richard Terrill is the executive vice president of marketing at XMOS. Prior to XMOS, he was vice president of marketing at Velogix, and, at Xilinx, was responsible for worldwide strategic marketing. He has held senior management positions at Lightspeed, Cadence, and Altera. He was a founder of RAPID, the IP business advocacy organization and was a corporate representative to the VSI Alliance. Terrill has a BS degree in physics from Rensselaer Polytechnic Institute. He may be reached at richard.terrill@xmos.com. 19 the target device. In the case of an FPGA, that’s a fairly simple process, supported by ample hardware. If the design is for a gate array or ASIC, there is an NRE and manufacturingtime price to pay. That means relatively little iteration is done with the HDL as it is expensive to evaluate accuracy in the actual target device. The goal of “ﬁrst time right” silicon is imperative, but it’s usually a “best attempt” constrained by time and budgets. Compare that with the process of loading a software object ﬁle into the target processor and allowing it to execute the code. It may even be able to self-evaluate the code with other concurrent applications that act as stimu- lus and analysis engines. Software-based designs that target a processor are inherently more stable than HDL-based designs that target gates for the following reason: the compiler has a few hundred opcodes and a few hundred variables to consider. A tiny 50K system-gate FPGA has half-a-million conﬁguration bits. And those bits are not exclusive, so the possible combinations are exponential. And a custom ASIC has as many options as there are atoms. Add to this the massively higher number of designs that go through software compilers and collectively add to the debugging process of the compiler. For these two factors alone, www.embedded.com/europe | embedded systems design europe | APRIL 2008 015-016-017-018-019_ESDE.indd 19 9/04/08 13:19:37 http://www.embedded.com/europe

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Embedded Systems Design Europe - April 2008 Contents Chip Industry Confronts 'Software' Gap Wind River's VxWorks OS Part of the nEUROn UCAV Demonstrator iSuppli Cuts Electronic Equipment Forecast Study Says GigE Vision Not Mature Chip Aids Wireless Health Monitoring Kontron Reports Strong Financial Growth Xilinx Completes Virtex-5 Line-Up French Project Builds Open Platform Home Automation Group Uses Enocean Radio Layer MIPs Adds Multi-Core Option to Portfolio Cover Feature: Next Gen Programmable Chips: Why Can't Hardware Be More Like Software? Improving Productivity & Quality With Domain-Specific Modeling Efficient CRC Calculation With Minimal Memory Footprint Do-It-Yourself Linux Embedded Development Tools Hardware/Software Verification Enters the Atomic Age New Products Advertising Contacts

Embedded Systems Design Europe - April 2008

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