Embedded Systems Design Europe - April 2008 - (Page 27)

crc calculation When implementing CRC in software, a common way of accelerating the calculations is through the use of lookup tables. This requires allocation of memory space that grows exponentially with increasing performance (generally, we need 2 rows of n bits each for p look ahead acceleration). However, if you are building a system based on the Blackﬁn processor, you can take advantage of some instructions included in the basic Instruction Set Architecture (ISA) speciﬁcally deﬁned for efﬁcient LFSR implementation. These instructions – BXOR and BXORSHIFT – offer excellent performance, without a requirement for lookup tables. This fact makes it ideal for use when available memory is in shortage. Using these instructions, one can calculate an External CRC at a rate of two cycles per input bit. The example program in Listing 1 shows how to use these instructions. This program consists of three functional parts. The ﬁrst part is the initialization code. Here, the LFSR state (A0) and the mask (A1), which contains the coefﬁcients of the generator polynomial, are initialized (Make sure to initialize the high byte of A1 as well). According to the deﬁnitions of an External LFSR as in Figure 2, A1’s lsb is populated with the generator polynomial’s high order coefﬁcient. In the above example program, the 32-bit message ﬁts into one register and is fed into the LFSR starting with the msb. The second part of the program is a loop of k iterations. In each iteration, one bit from the message is extracted and put in CC. Then, it is fed in and the LFSR state is updated according to the BXORSHIFT functional description (see the Blackﬁn instruction set documentation). That is, A0 is masked by A1, then the result is XOR-reduced and added to the input bit CC. The resulting bit is pushed into the lsb of A0 while the whole register is shifted to the left. In case the message is longer than 32-bits, a loop wrapping this part may be required, where a new data word is read into R2 from the message memory buffer. In the third part of the program, we use the second variant of BXORSHIFT, this time without feedback. However, p because in this variant the shift operation takes place prior to the XOR-reduction, we start by calculating the ﬁrst output bit with a BXOR instruction operating on the last state. Then we continue with loop of n-1 iterations. In each iteration, A0 is updated and a new output is put in CC. Then, the CRC register (R0) is shifted left with the CC bit put into its lsb. At the end of this part, R0 contains the n bits of the CRC string. Yaniv Sapir (yaniv.sapir@analog.com) is a project leader at the Digital Media Technology Center in Analog Devices, developing embedded media algorithms and software for ADI’s Blackﬁn processor. Yosef Stein (yosi.stein@analog.com) serves as DSP principal system architect/advanced technologies manager in the Digital Media Technology Center working on the development of broadband communication and image compression enhanced instructions for Analog Devices’ ﬁxed point DSPs. PowerTools are renowned for being a long term investment because of their open and modular architecture. PowerTrace II • 4 GByte of trace memory to record program and data flow • More than 40 processor architectures supported by the trace port USA Lauterbach Inc. www.lauterbach.com Germany Lauterbach GmbH www.lauterbach.de Great Britain Lauterbach Ltd. www.lauterbach.co.uk Italy Lauterbach Srl www.lauterbach.it China Suzhou Lauterbach Technologies Co., Ltd. www.lauterbach.cn Japan Lauterbach Japan Ltd. www.lauterbach.co.jp • Trace port speed up to 550 MHz • Sophisticated analysis methods to perform comprehensive performance analysis and quality assurance tests PowerDebug II • A Gigabit ethernet interface guarantees immediate display and rapid analysis of the trace information. www.embedded.com/europe | embedded systems design europe | APRIL 2008 27 024-025-026-027_ESDE.indd 27 8/04/08 12:47:29 http://www.lauterbach.com http://www.lauterbach.de http://www.lauterbach.co.uk http://www.lauterbach.it http://www.lauterbach.cn http://www.lauterbach.co.jp http://www.lauterbach.com http://www.embedded.com/europe

Table of Contents Feed for the Digital Edition of Embedded Systems Design Europe - April 2008

Embedded Systems Design Europe - April 2008 Contents Chip Industry Confronts 'Software' Gap Wind River's VxWorks OS Part of the nEUROn UCAV Demonstrator iSuppli Cuts Electronic Equipment Forecast Study Says GigE Vision Not Mature Chip Aids Wireless Health Monitoring Kontron Reports Strong Financial Growth Xilinx Completes Virtex-5 Line-Up French Project Builds Open Platform Home Automation Group Uses Enocean Radio Layer MIPs Adds Multi-Core Option to Portfolio Cover Feature: Next Gen Programmable Chips: Why Can't Hardware Be More Like Software? Improving Productivity & Quality With Domain-Specific Modeling Efficient CRC Calculation With Minimal Memory Footprint Do-It-Yourself Linux Embedded Development Tools Hardware/Software Verification Enters the Atomic Age New Products Advertising Contacts

Embedded Systems Design Europe - April 2008

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