Embedded Systems Design Europe - April 2008 - (Page 35)

veriﬁcation types such as arrays and FIFO queues to make the descriptions more readable. With proper abstractions, we can create TRS descriptions in a highly modular fashion. And using a compiler for hardware synthesis from TSRs, such descriptions can be translated into a standard hardware description language like Verilog. By restricting the generated Verilog to be structural, commercial tools can be used to go all the way down to gates and layout. The terms’ grammar, when augmented with details such as instruction formats and sizes of various register ﬁles, buffers, memories, and so on, precisely speciﬁes the state elements. Each rule is then compiled such that the state is read in the beginning of the clock cycle and updated at the end of the clock cycle. This single-cycle implementation methodology automatically enforces the atomicity constraint of each rule. All the enabled rules ﬁre in parallel unless some modify the same state element. In case of such a conﬂict, one of the conﬂicting rules is selected to ﬁre on the basis of some policy. An example of the power that the use of TSR atomicity brings to hardware synthesis is illustrated in Figure 2, in which Euclid’s algorithm for computing the greatest common divisor (GCD) of two numbers is expressed in explicitly and from scratch by the engineer in every instance. This makes these approaches: • • • Tedious, due to the ad hoc, low-level nature of managing concurrency. Error prone, subject to race conditions, interface protocol errors, mistimed data sampling (for hardware), deadlocks, among others. Brittle to changes, requiring the control to be redesigned each time there is a small change in the speciﬁcation or implementation. TSR notation. From this, the Term Rewriting Architectural Compiler generates a Verilog description of the circuit shown in Figure 3. ATOMICITY AND GENERATING HARDWARE/SOFTWARE How do atomic transactions such as those employed in TRSs contrast with other approaches used in software and hardware, such as with C/SystemC, Verilog, and VHDL? Contrasting these approaches with atomicity highlights just how low-level, manually intensive, and fragile these approaches are. In all of these other approaches, coordinating and managing the access to shared resources, which includes both arbitration and control, must be done Another issue with these approaches is that shared resource management is non-modular in nature, extending across module boundaries throughout system designs. Even if you ensure that individual modules operate properly from an atomic operation standpoint, you cannot use them as black boxes as you compose larger systems with them. Atomicity management requires control logic, and control logic is inherently non-modular. As you compose larger and larger systems, threads, events, always blocks and processes do not scale. Atomic transactions, in contrast, dramatically raise the level of abstraction by automatically managing the complex aspects of concurrency: shared resource arbitration and control. And, atomic transactions can be easily composed at a system level, allowing modules to be integrated as black boxes, without having to consider the impact of inter-module interactions on the internal resources of the modules. With atomic transactions, modulelevel testing can leveraged at the system level, without having to reverify that interface protocols at every interface point are properly being handled and remaining within required boundaries. IMPLICATIONS FOR EMBEDDED As a much higher level of abstraction for concurrency, atomic transactions are becoming available in areas that previously have not beneﬁted from their power. While widely available as a database tool, how are atomic transactions likely to surface for those writing embedded systems www.embedded.com/europe | embedded systems design europe | APRIL 2008 35 033-034-035-036.indd 35 8/04/08 12:35:49 http://www.embedded.com/europe

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Embedded Systems Design Europe - April 2008 Contents Chip Industry Confronts 'Software' Gap Wind River's VxWorks OS Part of the nEUROn UCAV Demonstrator iSuppli Cuts Electronic Equipment Forecast Study Says GigE Vision Not Mature Chip Aids Wireless Health Monitoring Kontron Reports Strong Financial Growth Xilinx Completes Virtex-5 Line-Up French Project Builds Open Platform Home Automation Group Uses Enocean Radio Layer MIPs Adds Multi-Core Option to Portfolio Cover Feature: Next Gen Programmable Chips: Why Can't Hardware Be More Like Software? Improving Productivity & Quality With Domain-Specific Modeling Efficient CRC Calculation With Minimal Memory Footprint Do-It-Yourself Linux Embedded Development Tools Hardware/Software Verification Enters the Atomic Age New Products Advertising Contacts

Embedded Systems Design Europe - April 2008

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