Embedded Systems Design Europe - April 2008 - (Page 7)

news adopted,” Hwu said. “Ultimately, I think we will make a small amount of extensions to C, but I think it’s too early. “If you really want to have a million people do something, don’t ask them to speak Latin. It is enough to ask them to just speak English without using cuss words,” he quipped, explaining the need for an evolutionary approach. Following that route, researchers from IMEC (Leuven, Belgium) described a handful of new tools based on what it called CleanC. Diederik Verkest, a group science director for the research institute, described it as a C variant that follows 28 “common sense” rules to smooth the path to parallelism. “Following these practices is a good thing to do if you want to have the best chance of analyzing your code,” said Verkest. One of the new IMEC tools aims to hide the complexity of new memory hierarchies and interconnect fabrics increasingly used in multicore chips. Another tool quickly shows scaling beneﬁts of a program without requiring the program to be debugged. “We believe compiler-like tools in the hands of smart programmers is the best way to get to parallel code,” said Verkest. Hardware moves on On the hardware front, MIPS Technologies came to the Expo with details of its ﬁrst multiprocessing-ready core. The 1004K aims to leapfrog existing products from its archrival ARM Ltd. For their part, Freescale and Intel sketched out design trends they see on the horizon for their multicore chips. Freescale is now sampling the ﬁrst dual-core versions of its PowerQuicc processors, aimed at telecom OEMs. The chips are part of a family that will eventually scale to 32-core devices, said Dan Cronin, vice president of R&D for Freescale’s networking division. The processors will use a new onchip interconnect fabric. They will also embed in hardware a hypervisor, a kind of low-level scheduling unit, co- Image: Dassault Aviation The nEUROn European Unmanned Combat Air Vehicle (UCAV) demonstrator will be standardized on Wind River’s VxWorks 653 operating system. The computer core system complies with the ARINC 653-1 avionics standard and can be supplied with complete RTCA DO-178B / EUROCAE ED-12B up to Level A certiﬁcation documentation. The objective of the nEUROn project is not to perform military missions, but to demonstrate maturity and effectiveness of technical and cooperation solutions. This technology demonstrator will have a number of aims including performing an air to ground mission, inserted in a network centric warfare; designing a stealth platform (radar cross section and infrared); and weapon delivery from an internal bay with stringent tempo constraint, The nEUROn UCAV demonstrator is being developed to demonstrate a modular and reliable avionics system, using commercial-off-the-shelf (COTS)-based modular on-board computers, and high-productivity and high-quality critical real-time software. The project is organized with Dassault Aviation as prime contractor in charge of the main contract implementation, and ﬁve European partners:·Alenia (Italy), SAAB (Sweden), Hellenic Aerospace Industry, EADS (Spain) andRUAG (Switzerland). Andi Pabinger, vice president of EMEA Sales for Wind River, said “We are seeing more unmanned systems developed internationally by disparate teams to meet increasingly diverse mission requirements. This growing complexity is driving the need for COTS components – including the software at the heart of unmanned vehicles.” developed with IBM according to specs set in the Power.org group. Freescale will release an open source reference design for companies that want to build virtualization software that taps into the hypervisor, Cronin said. “Several other processor companies are doing similar things” with embedded hypervisors, raising the issue of non-standard approaches to virtualization, said Marcus Levy, president of the Multicore Association and host of the expo. Intel described several extensions it sees on the horizon for its multicore chips, including new on-chip fabrics, scratchpad memories and use of spare cores and schedulers. “Beyond adding to the sheer number of cores, there are several system-level challenges that need to be overcome to tap into the true power of multicore processors,” said Pranav Mehta, chief technologist of Intel’s embedded group. Asked how many engineers Intel has working on multicore programming issues, Mehta said, “If I had to guess, I would say it is at least in four digits, but even Intel doesn’t think we can solve all the problems here alone.” A handful of chip startups, including Ambric and Intellasys, came to the expo touting novel multicore architectures and proprietary tools to write software for them. One of the newer companies among them, Plurality Ltd. (Netanya, Israel), said it will release a 256-core product early next year and simulation models and tools for using it in the next few months. 7 www.embedded.com/europe | embedded systems design europe | APRIL 2008 006-007_ESDE.indd 7 10/04/08 14:07:37 http://Power.org http://www.embedded.com/europe

Table of Contents Feed for the Digital Edition of Embedded Systems Design Europe - April 2008

Embedded Systems Design Europe - April 2008 Contents Chip Industry Confronts 'Software' Gap Wind River's VxWorks OS Part of the nEUROn UCAV Demonstrator iSuppli Cuts Electronic Equipment Forecast Study Says GigE Vision Not Mature Chip Aids Wireless Health Monitoring Kontron Reports Strong Financial Growth Xilinx Completes Virtex-5 Line-Up French Project Builds Open Platform Home Automation Group Uses Enocean Radio Layer MIPs Adds Multi-Core Option to Portfolio Cover Feature: Next Gen Programmable Chips: Why Can't Hardware Be More Like Software? Improving Productivity & Quality With Domain-Specific Modeling Efficient CRC Calculation With Minimal Memory Footprint Do-It-Yourself Linux Embedded Development Tools Hardware/Software Verification Enters the Atomic Age New Products Advertising Contacts

Embedded Systems Design Europe - April 2008

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