Embedded Systems Design Europe - May 2008 - (Page 13)

news Embedded developers cautious on multicore Embedded systems developers will make a slow transition to multicore processors, driven by a need for performance but concerned about difﬁculty programming the new chips and a lack of software standards. That was the result of an informal survey of 211 developers taken by software tool company Virtutech and Freescale Semiconductor at the Embedded Systems Conference. Only 51 percent of respondents said they have applications running on multicore CPUs or will migrate to multicore processors in the next 3-5 years. A whopping 49 percent said they neither use multicore chips nor plan to in the next ﬁve years. Seventy-ﬁve percent of respondents planning to use multicore chips said they are doing so to get more performance. But only 13 percent ranked performance as the most important factor in choosing a multicore CPU. Most (80 percent) said ease of programmability was the most important factor in choosing a multicore chip. Concerns about software rose to the top in terms of issues using multicore CPUs. Most respondents (50 percent) said a longer software development time was the key challenge in multicore. Another 25 percent said the top challenge was porting legacy code to the CPUs. Most respondents (58 percent) said they do not use a virtual prototyping tool when developing multicore applications. The remaining 42 percent were roughly split between those who do use such tools and those who plan to use them in the future. For those who use such tools, the lack of standards in virtual prototyping was the main concern for most respondents (49 percent). Indeed, multiple standards efforts are now trying to come to address standards for this emerging class of tools. The largest group of respondents who have developed multicore systems (38 percent) said their design cycles were between 12-18 months. The next largest group (26 percent) reported design times of 18-36 months. Altera launches D0-254 network In order to support the growing number of avionics and military applications requiring DO-254-certiﬁable components, Altera have launched a DO-254 Global Partner Network. Altera, together with Aldec, Geensys, HighRely and HCELL Engineering, provide a comprehensive environment of DO-254-certiﬁable intellectual property (IP) cores, in-hardware veriﬁcation ﬂows, and documentation. The inaugural partners provide specialty solutions and services that enable Altera FPGA and HardCopy ASIC solutions to be quickly approved and implemented in avionics and military applications. The DO-254 Global Partner Network targets customers requiring DO-254 Level A, B, C or D compliance. The DO-254 standard was developed by the avionics industry to establish hardware deployment guidelines for developers, veriﬁcation engineers, quality managers, installers and users. The standard provides design assurance and guidance for airborne electronic hardware designers, from conception through initial certiﬁcation and subsequent post-certiﬁcation product improvements to ensure continued airworthiness. The RTCA DO-254 standard deﬁnes ﬁve levels of criticality from level A (highest) to level E (lowest). These design assurance levels are required for all civil airborne electronic hardware. More recently, military airborne applications such as A400M are now requiring DO-254 compliance. The network provides military and avionics companies with a low-risk, highly efﬁcient design environment and validation process. Each partner brings solutions to the DO-254 design process, including veriﬁcation (Aldec), consulting, documentation and training (Geensys for Europe and HighRely for North America), and IP cores (HCELL Engineering). 13 Auto cooperation improves test Vehicle electronics test expert Berner & Mattner GmbH (Munich, Germany) has announced a cooperation with embedded software company PikeTec GmbH (Berlin). The move will expand the use cases for model-based real-time tests, the companies said. The cooperation enables automotive OEMs to create an integrated electronics test environment from test speciﬁcations through HiL (Hardwarein-the-Loop) test bench. In addition, it supports the reuse of existing test models, which signiﬁcantly increases the productivity of tests. The move aims at limiting the tendency towards drastically increasing the number of variants and the complexity of ECU tests, Berner & Mattner explained in a press release. Berner & Mattner plans to bring its Messina test automation platform while PikeTech will contribute its TPT graphical test case description environment. The combination of the two elements will also facilitate the cooperation between OEMs and tier-one vendors as well as between design department and test labs. Messina supports Tesis, Matlab/Simulink, Ascet models as well as Autosar components. www.embedded.com/europe | embedded systems design europe | MAY 2008 http://www.embedded.com/europe

Table of Contents Feed for the Digital Edition of Embedded Systems Design Europe - May 2008

Embedded Systems Design Europe - May 2008 Contents Microsoft Provides Embedded Roadmap Enea Buys Developers Irish Start-Up Raises Funds for Telecom FPGAs Kontron Promotes COM Express Nano Mentor Nucleus Platform Provides UI for Atmel Small Form Factor Boards Head for the SUMIT Proffibus Advances IO-Link Integration Embedded Developers Cautious on Multicore Auto Cooperation Improves Test Altera Launches DO-254 Partner Network Building an ‘Instant-Up’ Real-Time Operating Systems An Architecture for Reusable Embedded Systems Software Free up Bandwidth in PCI Express Evaluating Software in Medical Devices Circuit Sensitivity in Analog Circuits Choosing Flash Memory New Products Advertising Contacts

Embedded Systems Design Europe - May 2008

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