Embedded Systems Design Europe - May 2008 - (Page 37)

memory actors trying out for the role, choosing the right memory subsystem is much more complicated now, especially if you’re adding more multimedia functions to mobile and embedded systems while shrinking physical size and reducing overall system cost. Not only could the code and data storage needs have increased in these systems, but you’ve got to do it all more reliably with less of everything. Flash memory is the most practical solution, but knowing which type of ﬂash ﬁts best in a system is the key. Is NAND, NOR, managed NAND, or some hybrid the best choice? The use of NAND ﬂash, an inexpensive and high-density nonvolatile memory requiring defect management, to satisfy these growing code and data storage needs makes the memory subsystem even more complex. Add to that the need to support different memory types, interfaces, vendors, and vendor-speciﬁc features, and the memory subsystem even more complex. A completely managed memory subsystem solution can be designed that uses an industry-standard RAM (PSRAM or SDR/DDR SDRAM) interface. This managed memory subsystem would provide seamless integration with the host chipset/processor and eliminate the need for the host system to manage the complexity and deﬁciency of built-in memory devices. Unlike NAND ﬂash, NOR ﬂash is one of the oldest and the most widely used memory types in current embedded systems. It’s used for both code and data storage. Its main advantage is that the code is executed directly (execute-inplace) from the NOR ﬂash memory. Also, NOR ﬂash can directly interface with the host processor, which enables easy designin and fast time-to-market. With the increased deployment of multimedia functions in embedded systems, the need for code and data storage is also increasing. For these applications, using higher density NOR ﬂash for code and data storage becomes more expensive when compared with alternative solutions like NAND ﬂash. In addition, the highest density NOR ﬂash available today is 1 Gbit. Moreover, multimedia data storage requires both high read and write performance. As a result, system designers have turned to NAND ﬂash for storing multimedia ﬁles as well as application code in many embedded applications, including high-end cell phones. NAND FOR CODE & DATA STORAGE NAND ﬂash is well suited for applications that require large code storage (such as operating system and applications) and large data storage because NAND ﬂash is inexpensive and is also available in high densities (up to 16 Gbits in one die). Unlike NOR, NAND ﬂash doesn’t support execute in place (XIP) or random access. As a result, some systems that use NAND ﬂash need a low-density NOR ﬂash just for system boot-up and BIOS code execution. In other systems, a NAND ﬂash controller, or an embedded boot ROM in the host processor, can provide the boot function. After system boot-up, the NAND-based systems use either code shadowing or demand paging for code execution. In the case of code shadowing, the entire operating system and applications are copied from the NAND ﬂash into the system RAM, and in demand paging, a portion of the operating system and applications are copied into the system RAM as needed, where such code is then executed. Though NAND ﬂash is inexpensive and available in higher densities than NOR, NAND is less reliable and requires defect management, including error detection and correction, and wear-leveling to make it usable for many applications. These NAND ﬂash management functions require complicated hardware and software. Figure 1 shows a system where the host chip set interfaces with standalone NAND ﬂash. In this system, the defect management functions must be performed by the host chip set. Running such ﬂash management functions on the host requires some software development and it also uses some of the host’s CPU and memory resources, leading to a reduction in overall system performance. As NAND ﬂash vendors are moving to smaller process geometries, the ECC (error correction code) requirement for single-level cell (SLC) NAND ﬂash has increased from 1 to 4 bits per 512-byte sector, and for multi-level cell (MLC) NAND ﬂash, it’s increased from 4 to 8 bits per 512-byte sector. The page size has increased from 512 to 4,096 bytes. The endurance for some of the smaller geometry SLC NAND ﬂash has changed from 100,000 to 50,000 cycles, and for MLC NAND ﬂash it has changed from 10,000 to 5,000 cycles (and 3,000 cycles in some cases). To reduce the number of discrete components in the system, many chip set vendors have started integrating a NAND ﬂash controller in their chip set, which can directly interface with standalone NAND ﬂash. However, because of the long design cycle of a chip set, it’s difﬁcult for the chip set vendors to track the ever changing NAND ﬂash technologies. Therefore, the functionality of an embedded NAND ﬂash controller in the chip set will always lag the NAND ﬂash technologies. A few solutions are similar to standard NAND ﬂash, but offer improved performance and functionality. For example, OneNAND is a variation of NAND ﬂash that combines RAM and standalone SLC NAND ﬂash in one device to provide boot function and 37 www.embedded.com/europe | embedded systems design europe | MAY 2008 http://www.embedded.com/europe

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Embedded Systems Design Europe - May 2008 Contents Microsoft Provides Embedded Roadmap Enea Buys Developers Irish Start-Up Raises Funds for Telecom FPGAs Kontron Promotes COM Express Nano Mentor Nucleus Platform Provides UI for Atmel Small Form Factor Boards Head for the SUMIT Proffibus Advances IO-Link Integration Embedded Developers Cautious on Multicore Auto Cooperation Improves Test Altera Launches DO-254 Partner Network Building an ‘Instant-Up’ Real-Time Operating Systems An Architecture for Reusable Embedded Systems Software Free up Bandwidth in PCI Express Evaluating Software in Medical Devices Circuit Sensitivity in Analog Circuits Choosing Flash Memory New Products Advertising Contacts

Embedded Systems Design Europe - May 2008

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