Embedded Systems Design Europe - June/July 2008 - (Page 10)

news PLDs look to cut power budget and costs The normally quiet market for entry-level programmable-logic devices (PLDs) is suddenly heating up, with a price war possibly looming. Startup SiliconBlue Technologies Corp. could rock the boat with the rollout today of low-power, 65-nanometer ﬁeldprogrammable gate arrays for the handheld market. In a move to head off SiliconBlue at the pass, Xilinx Inc. reduced the price of a rival complex-PLD (CPLD) device to 50 cents per unit in mass quantities. Xilinx now claims to sell the world’s least-expensive FPGA/PLD, breaking a record said to be held by Actel, which has two FPGA products starting at 99 cents. Beyond price, the real key is which FPGA product can deliver the lowest static power for portable systems. The FPGA-based handheld market is a fast-growing sector that is expected to reach $650 million by 2010, according to Semico Research Corp. A new class of low-end FPGAs is needed, because “most FPGA products have not been able to hit the cost and power budget requirements” for battery-based handhelds, said Bryan Lewis, an analyst with Gartner Inc. (Stamford, Conn.). FPGAs and PLDs are not expected to displace baseband devices or application processors in handhelds. Rather, they are taking aim at ASICs and applicationspeciﬁc standard products. Low-end FPGA devices have long been used to provide the connectivity, interface and related glue-logic functions in a design. They sometimes serve as the interface between a particular chip and a baseband or application processor. But the new FPGA products “are clearly more than glue chips and provide functionality like other FPGAs,” 10 Lewis said. In high-end cell phones, they ofﬂoad the power consumption or another function in the baseband chip “and act like a coprocessor for a dedicated function.” Kapil Shankar, founder and chief executive of SiliconBlue (Sunnyvale, Calif.), said the new breed of FPGAs could provide the same functions for handhelds such as MP3 players and navigation devices. But the problem with traditional FPGA/PLD solutions is that they are unable to scale and have limited densities. “The bigger challenge is leakage” within these devices, said Shankar. Robert Blake, vice president of the consumer and automotive business at Altera (San Jose, Calif.), said the basic problem for OEMs is how to extend the battery life in handhelds. So the new class of FPGAs must address this issue while delivering smaller form factors, lower power consumption and cheaper prices. The FPGA/PLD sector is complex. Simple PLDs, which have relatively few logic elements or arrays, are used to build reconﬁgurable digital circuits. CPLDs consist of many programmable logic arrays linked by programmable interconnections. FPGAs have several complex intellectual- property (IP) logic blocks linked with lookup routing tables. Some of the newer parts have FPGA and CPLD traits. “We’ve made [FPGAs/PLDs] more cost-effective” for new and emerging lowpower handheld devices, said Richard Sevcik, a board member of SiliconBlue. Both Sevcik and CEO Shankar are former executives of Xilinx (San Jose). Based on Taiwan Semiconductor Manufacturing Co. Ltd.’s 65-nm low-power process, SiliconBlue’s devices incorporate FPGA-like lookup tables and a “nonvolatile conﬁguration memory” technology on the same chip. NVCM eliminates the need for an external ﬂash PROM device, said to be needed in rival products. Competitive offerings also use embedded ﬂash. In contrast, NVCM is an IP block based on a technology from SiliconBlue’s former parent, Kilopass Technology Inc. “NVCM is an oxide disruption technology based on one-time programmable memory. The devices themselves are SRAM FPGAs and are reprogrammable multiple times,” said John Birkner, vice president of strategic marketing for SiliconBlue. SiliconBlue’s entry-level iCE65L02 has 1,792 logic cells and up to 128 I/O pins. At 32 kHz, power consumption is as low as 25 microamps. The high-end iCE65L16, with 16,896 logic cells and up to 384 I/O pins, consumes 250 µA at 32 kHz. Meanwhile, Xilinx has lowered the price for its entry-level CPLD product to 50 cents at 500,000-unit quantities. The price cut involves only the XC2C32A Cool- Runner-II CPLD, consisting of 33 microcells and 33 I/Os. JUNE – JULY 2008 | embedded systems design europe | www.embedded.com/europe http://www.embedded.com/europe

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Embedded Systems Design Europe - June 2008 Contents Work in Progress to Define Compact PCI Plus Power.org Demonstrates New Tools Project Supports Multi-core System Programming Altium Links Electronic to Mechanical Design PLDs Look to Cut Power Budget and Costs Project to Provide Coverage Analysis Tool Microsoft Details Windows Embedded Update Cover Feature: Leveraging Virtual Hardware Platforms for Software Allocating Memory in MATLAB-to-C Code MDD & IDEs: Making the Twain Meet in Embedded System Designs Debugging Mixed Signal Designs for Infrequent & Random Events Why Open Source is the Natural Choice for High-security Systems Bringing the Benefits of Low Power CPUs to Modular Design New Products Advertising Contacts

Embedded Systems Design Europe - June/July 2008

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