Embedded Systems Design Europe - June/July 2008 - (Page 16)

cover feature ent optimizations. These are initially performed on the individual logical blocks inside of the hardware module. The optimizations range from simple algorithms, such as removing dead logic and constant propagation, to more complicated approaches such as duplicate-logic detection and replacement of certain logical operations with more efﬁcient equivalents. Once each of the blocks has been subjected to local optimizations the compiler logically elaborates the entire module. This elaboration phase exposes numerous additional optimization opportunities as the same algorithms that were applied to the individual logic blocks are now applied to the module as a whole. After the logic has been completely optimized, it’s scheduled into a set of execution sequences depending upon when it’s needed by hardware system. For example, if a block of logic is only ever accessed by logic that runs at 50 MHz, there is no need to constantly recalculate that logic based on the 250MHz logic that may feed into it. These execution sequences are ﬁnally mapped into code streams, which can be compiled into a single linkable object ﬁle. The hardware object itself is really only a part of what is needed by to create a useful virtual model. The object typically requires an integration layer to map its RTL-derived interface into one which is needed by the virtual platform. The level of abstraction represented by the virtual platform typically dictates what type of interface is required. A virtual prototype that is composed of cycle-accurate components will likely need only a simple adapter to map the pins of the hardware object into the data-types used by the platform, while virtual prototypes written at higher levels of abstraction will typically require a transactor to map system-level transactions into the multiple clock cycles of pin transitions necessary to model this behavior in hardware. A model compiler can often take advantage of its knowledge of the logic 16 contained in the design to automatically generate the wrapper code and transactors necessary to link the hardware object into the overall system and create a complete virtual model. This approach can be leveraged to target the same hardware object into multiple virtual prototypes at varying levels of abstraction depending upon the needs of user. HOW FAST WILL IT RUN? Once the virtual platform is assembled, the ultimate question is how fast will it run. The answer depends upon the level of accuracy of the models that comprise the platform. A platform consisting entirely of abstract models will execute quickly – sometimes faster than the real system – and allow for most high-level applications to be rapidly developed and debugged. Unfortunately, abstract models don’t have sufﬁcient hardware detail to allow lower-level software such as ﬁrmware and drivers to be fully developed and debugged. On the other end of the spectrum is a virtual platform constructed entirely from the hardware implementation model. The entire hardware description is simulated in conjunction with the system software. This has the implementation-level detail to develop all the software, but it will execute far too slowly to be of use for all but the most patient software engineer. An alternate approach combines the best aspects of both approaches. A hybrid virtual prototype combines the speed and versatility of the completely abstract model with the hardware accuracy of the implementation-level model. In a hybrid virtual prototype, the processing elements are typically represented using an instruction-set simulator (ISS). An ISS will typically execute the same binary executable as the real processor but will do so in a completely virtual manner. The remaining components in the hybrid virtual prototype are modeled at the abstraction level that best meets the goals of the software developer. In Figure 2, the memory subsystem is modeled in an abstract manner that enables the overall system to execute as quickly as possible but at the expense of cycle-level accuracy. The remaining components in the system were generated automatically from the RTL description. This combination maximizes the execution speed of the overall system but still delivers hardware accuracy for the components being addressed by the software. A hybrid virtual prototype can be constructed and reconﬁgured to meet the needs of the various constituent players in the validation lifecycle. Early in the design cycle of a system, the architect will typically require cycle-accurate components to make design de- JUNE – JULY 2008 | embedded systems design europe | www.embedded.com/europe http://www.embedded.com/europe

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Embedded Systems Design Europe - June 2008 Contents Work in Progress to Define Compact PCI Plus Power.org Demonstrates New Tools Project Supports Multi-core System Programming Altium Links Electronic to Mechanical Design PLDs Look to Cut Power Budget and Costs Project to Provide Coverage Analysis Tool Microsoft Details Windows Embedded Update Cover Feature: Leveraging Virtual Hardware Platforms for Software Allocating Memory in MATLAB-to-C Code MDD & IDEs: Making the Twain Meet in Embedded System Designs Debugging Mixed Signal Designs for Infrequent & Random Events Why Open Source is the Natural Choice for High-security Systems Bringing the Benefits of Low Power CPUs to Modular Design New Products Advertising Contacts

Embedded Systems Design Europe - June/July 2008

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