Embedded Systems Design Europe - June/July 2008 - (Page 6)

news Work in progress to deﬁne CompactPCI Plus The PCI Industrial Computer Manufacturers Group (PICMG) has formed a technical subcommittee to extend the current CompactPCI standard for both the 3U and 6U form factors mainly for applications in industry, avionics, transportation, and medical. It will also prove useful in telecom systems. The PICMG subcommittee members understand that CompactPCI Plus does not cover the same market segments as MicroTCA and the current CompactPCI standard lacks support of serial busses like PCI Express, Ethernet, SATA/ SAS and USB at the backplane. CompactPCI Express with support for PCI Express has no rear I/O and there is no cost effective migration path from CompactPCI without bridge slots. Switched fabrics shall not be required and thus not be deﬁned. The basic idea is to deﬁne a new peripheral slot supporting PCI Express as well as SATA/SAS, USB and Ethernet. Such slots can be used for PCI Express expansions, but also for hard disk raids, Ethernet switches, USB-based WiFi solutions. The idea is to support all modern busses on each peripheral board. A star architecture will be used to connect the system slot to the peripheral slots. An additional connector at the right-hand side, resulting in a two-slot system solution, shall extend the current 3U CompactPCI system slot. Currently available CPU products can be extended to support the serial busses on the second slot. A standard backplane would consist of legacy slots on the left-hand side, the system slot at the centre and the new peripheral slots on the right-hand side. If in the future legacy PCI will not be required, the system slot could be reduced to single slot. The system slot extension shall support a minimum of eight SATA/SAS lines, eight PCI express interfaces (x4 and minimum one by x16), 16 USB interfaces and 8 Ethernet channels. So all in all eight CompactPCI Plus peripheral slots are available. The connector for CompactPCI Plus must support differential highspeed signals. The data rate shall be minimum 10 Gbps to support also the next generation of serial busses such as SATA3.0, PCIE 2.0, USB 3.0 etc. 12 V at 8 Amps shall be supported for power supply. Mechanics shall be compliant to the current CompactPCI standard supporting 4-HP boards with unmodiﬁed front panels. Power.org debuts new tools Power.org, the open organization that develops and promotes Power Architecture technology, demonstrated three new tools at its Power Architecture Conferences in Munich, and Paris. The Power.org Solutions Portal inventories and categorizes the hundreds of Power Architecture product and service offerings that are readily available from the ecosystem of companies invested in the technology platform. The portal could be used by systems architects, systems designers, hardware and software developers, chip designers and integrators as their primary resource to locate the tools, software, hardware and services. The Power Architecture Early Tools Development Matrix is a listing of presilicon and systems development tools available for the Power Architecture platform. The Power.org Target Debug Capabilities Speciﬁcation deﬁnes a common set of debugging requirements for Power Architecture-based products. 6 An extension of the Power Instruction Set Architecture, this new speciﬁcation includes required and recommended debug features, functions and environments needed for single-core and multicore Power Architecture designs. “Until now, Power Architecture implementations lacked a uniform debug interface, environment and methodology, requiring tool vendors to develop multiple software and hardware conﬁgurations for different Power processors, SoCs and cores,” said Chris Ng, chairperson for Power.org’s Common Debug Interface Technical Subcommittee. “A common set of debug environments will ensure tool interoperability and reduce development costs.” Dr. Syed Ijlal Shah, co-chair for Power.org’s Technical Committee, added, “Both the Early Tools Development Matrix and the Target Debug Capabilities Speciﬁcation will ease design and accelerate the adoption of Power Architecture technology.” Project to support multicore system programming A consortium of nine industrial partners and research institutions has received a €4 million subsidy to conduct a three-year research project to simplify parallel programming by developing integrated Transactional Memory systems for multicore computers. The Velox project comes in response to the adoption of multicore chips for mainstream computing. Programs must be rewritten in a parallel way for computers with multiple processing cores, and coordination techniques such as ﬁne grained locking tend to be no longer applicable. Combining sequences of concurrent operations into atomic transactions “promises a great reduction in the complexity of both programming and veriﬁcation”, by making parts of the code appear to be sequential without the need to program ﬁne-grained locks. JUNE – JULY 2008 | embedded systems design europe | www.embedded.com/europe http://Power.org http://Power.org http://Power.org http://www.embedded.com/europe

Table of Contents Feed for the Digital Edition of Embedded Systems Design Europe - June/July 2008

Embedded Systems Design Europe - June 2008 Contents Work in Progress to Define Compact PCI Plus Power.org Demonstrates New Tools Project Supports Multi-core System Programming Altium Links Electronic to Mechanical Design PLDs Look to Cut Power Budget and Costs Project to Provide Coverage Analysis Tool Microsoft Details Windows Embedded Update Cover Feature: Leveraging Virtual Hardware Platforms for Software Allocating Memory in MATLAB-to-C Code MDD & IDEs: Making the Twain Meet in Embedded System Designs Debugging Mixed Signal Designs for Infrequent & Random Events Why Open Source is the Natural Choice for High-security Systems Bringing the Benefits of Low Power CPUs to Modular Design New Products Advertising Contacts

Embedded Systems Design Europe - June/July 2008

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