Embedded Systems Design - Europe - August/September 2007 - (Page 26)

test ing throughput has driven the evolution of parallel-bus structures to their practical limits. To gain more processing bandwidth, the PC industry is looking at high-speed serial interfaces, evidenced by the rapid growth of bus standards like PCI-Express. As the PC industry adopts serial interfaces, these technologies are becoming more accepted and entrenched. Implementation costs start dropping, which means serial interfaces are now making in-roads into lower-cost PC products and mainstream digital products – in other words, embedded systems. Once again, we see that evolutionary process: as embedded systems and their associated microprocessors pick up the new technology, design teams must adopt new development and debug methods to take advantage of highspeed serial interfaces. ADOPTING NEW METHODS Most of today’s digital designers are still accustomed to working with parallel buses and system clock speeds around 100 to 200 MHz. Well-developed standards, practices, and tools support such choices. However, high-speed (multi-gigabit) serial is another matter altogether. Design teams who successfully deploy high-speed serial are often now employing engineers with specialized skill sets focused on the physics of high-speed signal transmission (signal integrity). While this approach helps get products to market successfully, more development team changes are needed to successfully incorporate this advanced digital technology into designs destined for the mainstream digital electronics market. Teams need more knowledgeable designers along with the necessary tools and methods to handle this very different type of design problem. The ﬁrst step is to understand the design problem. How does designing a digital high-speed serial interface differ? Perhaps the most signiﬁcant difference is signal integrity. As the signal rates of key interfaces move into the gigabit 26 range, behavior occurs that has typically been the realm of the analog (or more likely RF/microwave) designer. Rather than being concerned about signal timing parameters, such as setup-and-hold and rise time, designers must deal with parameters such as eye opening, bit-error ratio, and jitter. ABILITY TO PROBE Also different is the ability to probe the signal one wishes to observe. This is a function of both the high integration levels seen in today’s silicon as well as the need to manage the integrity of the signal path very carefully. As speeds rise above 3 Gbits/s, it becomes necessary to apply pre-transmission conditioning to the signal to compensate for the transmission medium’s lossy effects; handling the signal at the receiver thus requires the corresponding ﬁltering to accurately recover the signal. Also, because these signals often operate in the low-power environments of sub-micron digital silicon, voltage swing is small. This means that simply attaching a physical probe, in traditional test and measurement fashion, becomes virtually impossible because the probe itself signiﬁcantly disrupts the signal. Testing and debugging these interfaces must allow for the real-world effects these factors create. The need to focus on signal integrity indicates that digital designers must incorporate new measurement types (and tools) into their standard tool box of tests they use to validate these designs. Sophisticated tools that measure signal integrity and characterize things such as eye metrics, bit-error ratio (BER), and jitter tolerance are becoming more common and must evolve from their once-specialized role into more mainstream offerings. Approaches must evolve to allow for probing these critical signals given their sensitive nature and the high integration levels seen in today’s silicon implementations. EMBEDDED TEST IS THE ANSWER As with the emergence of on-chip debug tools and techniques in the microprocessor world, the answer, at least to the probing problem, is to implement more of the test functions in the silicon itself. Because the signal path is by deﬁnition managed carefully by the chip developers, incorporating the ability for the application designer to make key measurements and observe the serial interface’s behavior can best be handled AUGUST – SEPTEMBER 2007 | embedded systems design europe | www.embedded.com/europe 025-026-028-029_ESDE.indd 26 5/09/07 13:07:21 http://www.embedded.com/europe

Table of Contents Feed for the Digital Edition of Embedded Systems Design - Europe - August/September 2007

Contents News Cover Feature: Annual Study Uncovers the Embedded Market DSP Serves the Convergence Needs of Small Business Embedded Test Offers Unique Value for Serial I/O The Software Detective: First-Fault Data Capture Boards May Shrink But Performance Doesn't New Products Advertising Contacts

Embedded Systems Design - Europe - August/September 2007

For optimal viewing of this digital publication, please enable JavaScript and then refresh the page. If you would like to try to load the digital publication without using Flash Player detection, please click here.