Embedded Systems Design - Europe - August/September 2007 - (Page 28)

test in this way. This method, called embedded test, eliminates the need to attach an external probe (with its associated problems) and allows access to information about the signal (such as the actual eye metrics recovered by the receiver) that wouldn’t be available externally. A real example of this is shown in Figure 1. Here, measurements made on a serial link operating at 6.25 Gbits/s show that even if physical probing limitations can be overcome, observing the signal at the device’s pins yields confusing information due to the application of pre-transmission signal conditioning. Simply by looking at just this information, one might conclude that the link isn’t operating because no signal eye can be observed. However, by incorporating on-chip measurement, as seen in the view on the right of Figure 1, engineers can determine that a signal is indeed being recovered by the receiver. THE FPGA’S ROLE As serial technology emerges in the realm of embedded systems, the FPGA plays a signiﬁcant role. FPGAs have long been a key implementation technology for embedded systems designers, and the role of FPGAs is increasing as they evolve to new price-performance levels. FPGAs are increasingly becoming an integration platform with system-on-chip (SoC)-like capability implemented in a programmable infrastructure. This gives embedded systems designers lots of ﬂexibility and a relatively low-cost approach for achieving high levels of integration in their designs. FPGA vendors also realize the trend toward serial interfaces and are working to bring usable high-speed serial technology into the hands of more developers. Most high-end FPGA families now incorporate multi-gigabit serial I/O capability, a feature that’s making its way into some of the lower-cost device families offered by FPGA suppliers. The FPGA’s inherent reprogrammability also provides a unique opportunity for tools that implement test functions. Development and test tools are emerging that give designers new ways to get insight into the behavior and quality of their serial interfaces. These new tools use measurement types corresponding to high-speed serial requirements (such as BER measurement), making them available to entire classes of designers who may not have considered them previously due to domain knowledge and the cost to obtain the associated instruments. TESTING HIGH-SPEED SERIAL I/O Tools are available to allow FPGA developers to measure serial I/O. A block diagram of such a tool is shown in Figure 2. The tool consists of three basic components: 1. A test core that implements on-chip test pattern generation, BER measurement, and access to transmitter and receiver control registers; 2. Measurement software; and 3. A simple hardware interface, in this case implemented with the JTAG programming cable. With this architecture, one can see that by conﬁguring these three components properly, a measurement can be set up to get insight into the operation of a high-speed serial link implemented with Xilinx FPGAs. Such a tool provides the ability to make three basic link measurements, all based on BER, which is widely accepted as the deﬁnitive measure of high-speed serial interface operation. At its simplest, the tool can provide link BER measurement. This measurement is made internally and reﬂects the actual conditions seen by the receiver inside the FPGA, not using a probe attached at the pins of the device as with a more conventional measurement. Another measurement of interest, is eye mapping (shown in Figure 3), which provides a simple way to quickly assess link margin. By making repeated BER measurements across the unit interval of the data eye, the user is presented with a graph of the BER versus the position in the eye. And ﬁnally, by combining the eye mapping capability with access to the transmitter and receiver control registers, the ability to actively tune the link for optimal BER is provided. 28 AUGUST – SEPTEMBER 2007 | embedded systems design europe | www.embedded.com/europe 025-026-028-029_ESDE.indd 28 5/09/07 13:07:36 http://www.embedded.com/europe

Table of Contents Feed for the Digital Edition of Embedded Systems Design - Europe - August/September 2007

Contents News Cover Feature: Annual Study Uncovers the Embedded Market DSP Serves the Convergence Needs of Small Business Embedded Test Offers Unique Value for Serial I/O The Software Detective: First-Fault Data Capture Boards May Shrink But Performance Doesn't New Products Advertising Contacts

Embedded Systems Design - Europe - August/September 2007

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