Embedded Systems Design Europe - August/September 2008 - (Page 35)

multicore consolidate this design philosophy. Further, emergence of IP-provider business models catalyzed the standardization of IP interconnect and design methods to facilitate design reuse centered on an open standard. However, localized bus transactions, as conducted through OCP interconnect segments, decouple processors throughout a multicore cluster. Coherence schemes cannot be directly based on bus snooping and reliance on bus arbitration to ensure access ordering. Different methods of communication are needed to ensure data is accessed consistently. Additional challenges arise in the ordering of competing L1-line data requests. One way to address these challenges is to add coherence-message communication to each processing element as depicted in Figure 1 in a system MIPS calls a Coherent Processing System (CPS). This system provides the means of snoop-type cache coherence. Coherence messages embody a new type of command within the OCP protocol. Members of the processor system send coherence messages toward a centralized coherence manager that provides access ordering (serialization) and message routing to provide snoop-type access to peer members. These peers will respond with their individual L1-line status and post a message response. Depending on responses, the coherence manager initiates data movement for coherent data among cores and funnels access toward higher-level memory hierarchies such as L2 and L3 caches. I/O coherence units also provide a means to phase-in/out data toward/from the coherent address space and are part of coherent-message exchange. In addition to new message-type commands within the OCP protocol, individual processors are required to respond to coherent status requests and are therefore not solely initiators (masters) of bus transactions. The CPS Different methods of communication are needed to ensure data is accessed consistently. might address this requirement by providing an OCP slave port to receive and respond to messages initiated by the coherence manager. Coherent requests by a processor will use the OCP master port. Within the processing cluster, coherence-message exchanges between cores and the coherence manager are dubbed interventions. OCP slave ports of processors receiving interventions are therefore intervention ports. As depicted in Figure 1, each individual processor of the MIPS 1004K system is based on our multithreaded processor architecture, providing two independent threads and processing context within the envelope of a single-scalar, 9-stage pipeline. Level 1 data-cache tag arrays are duplicated to be accessible simultaneously for CPU operation and intervention lookup. MESIstyle cache-line coherency is supported. The coherence manager of the processing system receives and serializes incoming messages through its request unit – OCP slave ports, driven by each CPU and I/O-coherence units. Serialized messages are routed depending on their address space and context either to higher-level cache hierarchies using the memory interface unit, or toward processor peers and I/Ocoherence units using the snoop agent. The snoop agent initiates OCP master transactions (interventions) to look up the coherent L1 cache-line status for each processor. Interventions returned to the initiator of a message, called self-interventions, allow the initiator to provide access ordering. Responses to coherent messages initiated by CPUs as well as data responses are formulated within the response unit and routed to individual CPUs. COHERENT OCP COMMANDS OCP commands used within the 1004K CPS can be classiﬁed into three categories: • Coherent messages maintain a MESI-style cache-line status. These messages are a result of CPU load 35 www.embedded.com/europe | embedded systems design europe | AUGUST – SEPTEMBER 2008 034-035-036-037_ESDE.indd 35 28/08/08 12:13:39 http://www.embedded.com/europe

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Embedded Systems Design Europe - August/September 2008 Contents TI Overhauls DSP Lineup, Adds 15 Processors QNX Publishes Source Code for File System Congatec to Take on Proprietary Market Swiss Multicore Project Wins Microsoft Grant OpenCores Bundles Development Tool ARM Compiler Boosts Freescale i.MX31 LabVIEW Updated for Multicore and Wireless Cover Feature: Interactive Tool Supports Multiprocessor SoC Design Wanted: Benchmaking for Embedded VMM Hypervisors Graphical Design Empowers Spider Robots Building a Power Supply for Discontinuous Transmission Wireless Networks RTOS Selection & Best Practices Achieving Cache Coherence in a MIPS32 Multicore Design New Products Advertising Contacts

Embedded Systems Design Europe - August/September 2008

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