Embedded Systems Design Europe - August/September 2008 - (Page 36)

multicore and store operations and can initiate data movement between CPUs and the memory subsystem. All peer CPUs of the CPS will receive coherent messages posted by an initiator and respond according to their cache-line coherent state. The coherence manager will initiate data movement as required. Coherent cache-manipulation commands are used for cache-line maintenance within the coherent address space. I/O trafﬁc will bring new coherent lines into the domain or remove coherent context from cache lines. Further, operations that synchronize memory hierarchy are performed. Noncoherent commands perform OCP main-port transactions on memory regions outside the coherent address space. These represent OCP read and write commands. this message as an OCP master-port command. Peer CPUs of the system receive interventions based on this linestatus change and will respond with their local cache-line status. The ﬁrst message type is the CohReadOwn, denoting a cache miss that occurred through an attempt to modify a cache line. As Figure 2 shows, peer cores encountering this line in status “Modiﬁed” will force a write-back into the memory subsystem and perform a local invalidate. As an optimization, locally encountered line data will be forwarded to the requester CPU to reduce access latency. The requester CPU will install this line as “Exclusive” and perform the line-modifying instruction. Then the cache-line status will change to “Modiﬁed.” While waiting for line reﬁll, the requester CPU will continue execution of another thread. The CohReadShared message indicates that a cache miss occurred through a line read operation. No line modiﬁcation is intended. As Figure 3 shows, peer cores encountering this line in status “Modiﬁed” will force a write-back into the memory subsystem. Hitting peer lines will migrate to “Shared” status. Hit data is forwarded to the requester core and installed in state “Shared.” Then the line read operation is performed. While waiting for line reﬁll, the requester CPU will continue execution of another thread. CohUpgrade indicates that a linemodifying instruction encountered a cache hit on a “Shared” line. As Figure 4 shows, peer cores will be notiﬁed to invalidate hitting lines. The “Shared” line is then upgraded to “Modiﬁed” after the modifying instruction is executed. Finally, the CohWriteBack message signiﬁes eviction of a coherent cache line. The coherence manager will initiate data movement through the intervention port and forward data to the memory subsystem. The evicted cache line is then replaced by a new – possibly coherent – address. In this case, a CohReadOwn or CohReadShared has caused the eviction. COHERENT CACHE MANIPULATION COMMANDS In response to cache manipulations, coherence messages are initiated and sent to peers. CohCopyBack – write back a coherent cache line to the memory subsystem. Cache-line hits in state “Modiﬁed” will be written back. Line status migrates to “Shared.” CopyBack data movement will be initiated by the coherence manager using the intervention port. CohInvalidate – purge a coherent cache line without writing back its contents to the memory subsystem. This command is always data-less and is posted to each peer of the CPS. Invalidate-type cache operations cause a CohInvalidate message. CohWriteInvalidate – an I/O coherence unit injects a new cache line into the coherent domain. Existing peer line data will be invalidated throughout the CPS. CohReadInvalidate – an I/O coherence unit notiﬁes the system about a cache line leaving the coherent domain. 36 AUGUST – SEPTEMBER 2008 | embedded systems design europe | www.embedded.com/europe • • COHERENT MESSAGES The CPS may implement four coherent messages that are caused by L1 cacheline-status changes due to CPU load and store activity. The initiating CPU sends 034-035-036-037_ESDE.indd 36 28/08/08 12:14:31 http://www.embedded.com/europe

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Embedded Systems Design Europe - August/September 2008 Contents TI Overhauls DSP Lineup, Adds 15 Processors QNX Publishes Source Code for File System Congatec to Take on Proprietary Market Swiss Multicore Project Wins Microsoft Grant OpenCores Bundles Development Tool ARM Compiler Boosts Freescale i.MX31 LabVIEW Updated for Multicore and Wireless Cover Feature: Interactive Tool Supports Multiprocessor SoC Design Wanted: Benchmaking for Embedded VMM Hypervisors Graphical Design Empowers Spider Robots Building a Power Supply for Discontinuous Transmission Wireless Networks RTOS Selection & Best Practices Achieving Cache Coherence in a MIPS32 Multicore Design New Products Advertising Contacts

Embedded Systems Design Europe - August/September 2008

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