Embedded Systems Design Europe - August/September 2008 - (Page 37)

multicore Existing peer line data will be invalidated throughout the CPS. CohCompletionSync – data-less command to maintain ordering. Local buffers of CPS peers are ﬂushed towards the memory subsystem. The CPU-SYNC instruction causes the CohCompletion-Sync for CPUs attending the coherent domain. SYNC command arguments (sync types) help control the depth of ﬂush operations throughout memory hierarchies. The CPS reserves certain argument encodings to support low-overhead access ordering. NONCOHERENT COMMANDS Traditional OCP commands such as “Read” and “Write” are supported throughout the CPS to handle data access for noncoherent memory access. The Read command is issued when a miss within a cached, noncoherent address or an uncached access causes a read operation from the memory subsystem. Response data – if cacheable – will be installed as noncoherent, whereas uncached data are consumed directly. Fetch as well as load and store activity causes Read transactions. The Write command is issued when cached, noncoherent eviction data or uncached-address-range stores will be written back to the memory subsystem. The OCP main port of a core performs the command and data phases of the transaction. OCP WORKS WELL FOR CPS The OCP interconnect lent itself well to support message-based coherence implementations. A centralized coherence manager serializes coherence messages emanating from an individual core and inquires about the coherence status of peer cores. Data forwarding between cores decreases access latency and reduces trafﬁc to higher levels of memory hierarchy. Individual cores possess an OCP master port to initiate data access and an OCP slave port to receive inquiries from the coherence manager. Matthias Knoth (knoth@mips.com), a design engineer for MIPS Technologies, Inc., is responsible for low-power microarchitecture and 1004K processor implementation. Knoth has more than 13 years experience in the semiconductor industry and holds a masters in electronics from the University of Technology, Chemnitz, Germany. www.embedded.com/europe | embedded systems design europe | AUGUST – SEPTEMBER 2008 37 034-035-036-037_ESDE.indd 37 28/08/08 12:14:52 http://www.embedded.com/europe

Table of Contents Feed for the Digital Edition of Embedded Systems Design Europe - August/September 2008

Embedded Systems Design Europe - August/September 2008 Contents TI Overhauls DSP Lineup, Adds 15 Processors QNX Publishes Source Code for File System Congatec to Take on Proprietary Market Swiss Multicore Project Wins Microsoft Grant OpenCores Bundles Development Tool ARM Compiler Boosts Freescale i.MX31 LabVIEW Updated for Multicore and Wireless Cover Feature: Interactive Tool Supports Multiprocessor SoC Design Wanted: Benchmaking for Embedded VMM Hypervisors Graphical Design Empowers Spider Robots Building a Power Supply for Discontinuous Transmission Wireless Networks RTOS Selection & Best Practices Achieving Cache Coherence in a MIPS32 Multicore Design New Products Advertising Contacts

Embedded Systems Design Europe - August/September 2008

For optimal viewing of this digital publication, please enable JavaScript and then refresh the page. If you would like to try to load the digital publication without using Flash Player detection, please click here.