Embedded Systems Design Europe - October 2007 - (Page 31)

microcontrollers Listing 6 The general strategy of transitioning to a low-power mode for ARM-based MCUs (IAR ARM compiler, AT91SAM MCU)4. __disable_interrupt(); /* disable interrupts at the ARM-core level */ if (idle_condition()) { /* idle condition reached? */ AT91C_BASE_PMC->PMC_SCDR = 1; /* Power-Management: disable CPU clock */ __enable_interrupt(); /* enable interrupts at the ARM-core level */ } else { /* idle condition not reached yet */ __enable_interrupt(); /* enable interrupts at the ARM-core level */ } the machine doesn’t automatically return to the low-power mode, but rather the background loop can continue after the ISR restores the SR from the stack as part of the return from the interrupt. Luckily, this is quite simple with the intrinsic functions provided by most C compilers for the MSP430. Listing 3 shows the ISR example for the GNU gcc compiler for MSP430. AVR Atmel’s AVR low-power 8-bit RISC also provides a method for atomic transition to the sleep mode, but it’s less obvious than in the case of HC08 or MSP430. The AVR core provides a SLEEP instruction to stop the CPU clock, but it doesn’t enable the interrupts and, in fact, must be executed with interrupts enabled. This would be a problem, if not for the following obscure note in the AVR datasheet:3 “When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example: SEI; set Global Interrupt Enable SLEEP; enter sleep, waiting for interrupt ; note: will enter sleep ; before any pending interrupt(s) . . .” Listing 4 is a C example for the IAR AVR compiler that shows how to enter the sleep mode from the background loop. The same example for the GNU AVR (WinAVR) compiler is shown in Listing 5. ARM ARM-based MCUs take a different approach to the atomic low-power transition. The ARM silicon vendors, such as Atmel, NXP (formerly Philips), and TI, integrate the standard ARM7 or ARM9 cores with the set of proprietary peripherals, such as the interrupt and power-management controllers. The integration is loose in that the ARM core’s internal state doesn’t impact the peripherals. In particular, the core can disable interrupts internally by setting the I and F bits in the current program status register (CPSR), but it doesn’t effect the external power-management or interrupt controller, which provide another layer for disabling and enabling interrupts. Because of this design, the ARMbased MCUs allow transitioning to a low-power mode with interrupts disabled at the ARM-core level. Upon In other words, the pair of instructions SEI-SLEEP is guaranteed to execute atomically, most likely due to the AVR pipeline structure. Be careful to always use the SEI-SLEEP pair of instructions together, never separated by any other instruction. www.embedded.com/europe | embedded systems design europe | OCTOBER 2007 31 028-029-030-031-032-033-034_ESDE31 31 10/10/07 11:37:48 http://www.dvsinc.com http://www.dvsinc.com http://www.embedded.com/europe

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Embedded Systems Design Europe - October 2007 Contents Linux Set to Dominate Torvalds Updates Linux Kernel ARM Establishes Smart Card Foundry Program Emerson Buys Motorola's Embedded Comms Group LynuxWroks and TTTech to Cooperate on Avionics MontaVista CEO Looks for Acquisitions in Europe Ready: Multiprocessing Technology Provides Opportunity Automotive to Drive MCU Market New Supporters Join COM Express Group Analyst Weighs TI Versus Xilinx Versus PicoChip Cover Feature: Embedded Systems Security Has Moved to the Forefront Trace Exposes the Toughest Real-Time Bugs Employ a Secure Flavor of Linux Use an MCU's Low-Power Modes in Foreground/Background Systems Transporting Video Over Wireless Networks New Products Advertising Contacts

Embedded Systems Design Europe - October 2007

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