Embedded Systems Design Europe - October 2007 - (Page 32)

microcontrollers Listing 7 The atomic transition to the sleep mode for the Cortex-M3 (IAR ARM compiler). __disable_interrupt(); if (idle_condition()) { __asm(“WFI”); __enable_interrupt(); } else { __enable_interrupt(); } /* /* /* /* __asm(“CPSID i”); */ idle condition reached? */ stop the CPU and Wait-For-Interrupt */ __asm(“CPSIE i”); */ /* idle condition not reached yet */ /* __asm(“CPSIE i”); */ such a transition, the power-management controller stops the CPU clock for the ARM core, but any interrupt enabled at the interrupt controller level can start the CPU clock. When the core starts running again, it can enable interrupts to achieve low interrupt latency. Listing 6 shows the general strategy of transitioning to a low-power mode for ARM-based MCUs (IAR ARM compiler, AT91SAM MCU).4 The power-management controller stops the CPU clock (AT91C_BASE_PMC>PMC_SCDR = 1) while the interrupts are disabled at the core. The interrupts are enabled only after the CPU wakes up again and executes the __enable_interrupt() intrinsic function. You can see this behavior if you try to break into a running application with a JTAG-based debugger. Usually, the code will stop at the __enable_interrupt() line. Speaking of debugging, the sleep mode can interfere with many on-chip debuggers because it stops the CPU clock. Therefore, you must use conditional compilation to include the lowpower transition only in the non-debug (production) version of the code. CORTEX-M3 Cortex-M3 is ARM’s 32-bit RISC architecture designed for low-cost and low-power mobile applications. It differs from the traditional ARM7 or ARM9 cores in a few ways. The main difference relevant to this discussion is a tighter integration of the MCU core with the system power management and the nested vectored interrupt controller (NVIC). The Thumb-2 instruction set, used exclusively in the Cortex-M3, provides a special instruction WFI (wait for interrupt) for stopping the CPU clock. Unfortunately, the reference manuals (the ARMv7-M Reference Manual, the Cortex-M3 Technical Reference, or the LM3Sxxx data sheets)5–7 don’t describe whether the WFI instruction can be used with interrupts disabled. Given this lack of information, I was forced to experiment with the actual Cortex-M3 MCU. Using the LM3S811 Cortex-M3 MCU from Luminary Micro, I discovered that the WFI instruction can be used while interrupts are locked (the PRIMASK register set to one). As expected, after the WFI instruction, the LM3S811 stops executing code, but any interrupt en- abled in the NVIC wakes the CPU up. Listing 7 shows the atomic transition to the sleep mode for the Cortex-M3 (IAR ARM compiler). 8051 The 8051 architecture supports two low-power levels (idle and power down). These modes are activated by setting the IDL or PD bits in the power control register PCON at the address 0x87. Writing to the IDL or PD bit stops the CPU immediately and must happen with interrupts enabled, otherwise the 8051 locks-up. This means that it’s impossible to transition to one of these modes atomically. Any enabled interrupt can preempt the idle processing after the interrupts are enabled, but before the idle mode is entered. Clearly, the 8051 requires a different technique than those discussed so far. This other technique is to invalidate the idle mode transition in every interrupt. So, if an interrupt preempts the background loop just before the indented transition to idle, the ISR will disable the transition. After the interrupt returns, the idle mode is not entered. One way of implementing this Listing 8 How the background loop uses the PCON_shadow variable (for the Keil C51 compiler). unsigned char bdata PCON_shadow; EA = 0; if (idle_condition()) { PCON_shadow = PCON | 0x01; EA = 1; PCON = PCON_shadow; } else { EA = 1; } /* allocate PCON_shadow in bdata area */ /* /* /* /* /* lock interrups */ idle condition reached? */ set the IDL bit in the shadow */ unlock interrupts */ go to idle (single instruction: MOV 87H,20H) */ /* idle condition not reached yet */ /* unlock interrupts */ 32 OCTOBER 2007 | embedded systems design europe | www.embedded.com/europe 028-029-030-031-032-033-034_ESDE32 32 10/10/07 11:38:03 http://www.embedded.com/europe

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Embedded Systems Design Europe - October 2007 Contents Linux Set to Dominate Torvalds Updates Linux Kernel ARM Establishes Smart Card Foundry Program Emerson Buys Motorola's Embedded Comms Group LynuxWroks and TTTech to Cooperate on Avionics MontaVista CEO Looks for Acquisitions in Europe Ready: Multiprocessing Technology Provides Opportunity Automotive to Drive MCU Market New Supporters Join COM Express Group Analyst Weighs TI Versus Xilinx Versus PicoChip Cover Feature: Embedded Systems Security Has Moved to the Forefront Trace Exposes the Toughest Real-Time Bugs Employ a Secure Flavor of Linux Use an MCU's Low-Power Modes in Foreground/Background Systems Transporting Video Over Wireless Networks New Products Advertising Contacts

Embedded Systems Design Europe - October 2007

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