Embedded Systems Design Europe - October 2007 - (Page 33)

microcontrollers Listing 9 The PCON shadow must be updated in every ISR that can produce work for the background loop. void my_ISR(void) interrupt xx { PCON_shadow = PCON; } /* update the PCON shadow */ Listing 10 Deﬁne a 4-byte array in RAM. This machine code represents a tiny C-callable function that executes the WAIT instruction and returns to the caller. unsigned int volatile Wait_code[] = { 0xF37D, /* WAIT instruction (M16C is little endian) */ 0x04F3 /* RTS,NOP instruction pair (M16C is little endian) */ }; technique on the 8051 is to shadow the PCON register allocated in the 8051’s bit-addressable memory (bdata). Let’s call this variable PCON_shadow. Listing 8 (for the Keil C51 compiler) shows how the background loop uses the PCON_shadow variable. The background loop sets the IDL bit only in the PCON_shadow variable when the interrupts are still disabled. Then, interrupts get enabled and the register PCON is restored from the shadow. It’s important that the PCON register’s update occurs in one machine instruction. As it turns out, the simple assignment of a bit-addressable variable to the special register, such as PCON, can be accomplished in one instruction – MOV 87H,20H. The PCON shadow must be updated in every ISR that can produce work for the background loop, as shown in Listing 9. Note that the 8051 clears the IDL/PD bits in the PCON register before entering any interrupt, so these bits are guaranteed to be cleared in the shadow register when it’s updated from PCON in the interrupt context. With this design, an interrupt can occur at any machine instruction between enabling interrupts until restoring the PCON register from the shadow PCON_shadow. Any such interrupt will clear the IDL/PD bits in the PCON_ shadow variable, so the bits won’t survive to the point when the background loop actually restores PCON from the shadow. Any interrupt that preempts the idle loop disables the idle mode, which accomplishes the goal of an interrupt-safe transition to idle mode. M16C The M16C 16-bit processor from Renesas supports the low-power wait mode, which is entered using a special WAIT instruction. However, the M16C datasheet is very speciﬁc that interrupts must be enabled before executing the WAIT instruction, so clearly the M16C doesn’t support an atomic transition to the wait mode.8 The M16C datasheet contains no side notes similar to the AVR note about atomic execution of the SLEEP-SEI instruction pair, so I assume that the interrupt-disable instruction (FCLR I) is effective immediately. Like the 8051, the only option for the M16C is to somehow disarm the transition to the wait mode in the ISRs, to prevent the background loop from entering the wait mode just after an interrupt. In contrast to the 8051, however, the M16C accomplishes the low-power mode transition using a special instruction, not through a write to a register, so the shadow register technique doesn’t apply. The idea of disarming the wait- 028-029-030-031-032-033-034_ESDE33 33 10/10/07 11:38:16 http://www.syslogic.com http://www.syslogic.com

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Embedded Systems Design Europe - October 2007 Contents Linux Set to Dominate Torvalds Updates Linux Kernel ARM Establishes Smart Card Foundry Program Emerson Buys Motorola's Embedded Comms Group LynuxWroks and TTTech to Cooperate on Avionics MontaVista CEO Looks for Acquisitions in Europe Ready: Multiprocessing Technology Provides Opportunity Automotive to Drive MCU Market New Supporters Join COM Express Group Analyst Weighs TI Versus Xilinx Versus PicoChip Cover Feature: Embedded Systems Security Has Moved to the Forefront Trace Exposes the Toughest Real-Time Bugs Employ a Secure Flavor of Linux Use an MCU's Low-Power Modes in Foreground/Background Systems Transporting Video Over Wireless Networks New Products Advertising Contacts

Embedded Systems Design Europe - October 2007

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