Embedded Systems Design Europe - October 2007 - (Page 40)

new products Serial analyzers ready to test PCI Express 2.0 The Tektronix TLA7S16 and TLA7S08 Serial Analyzers are for test and validation of PCI Express (PCIe) 1.0 and 2.0 designs and provide detailed PCIe 2.0 protocol information along with crossbus analysis. PCI Express 2.0 introduces a speed increase from 2.5 Gb/s to 5.0 Gb/s. The most signiﬁcant validation challenges for PCIe 2.0 are capturing the signal at twice the speed, verifying power management, and performing cross-bus analysis. For power management, the number of lanes in use or “link width” (up to 16 lanes), speed of the link (from 2.5 Gb/s to 5.0 Gb/s), and idle states are dynamically negotiated to conserve power whenever possible. PCIe 2.0 is a three layered architecture with physical (electrical and logical sub-blocks), data link and transaction layers. The link width, initialization, and speed negotiation is performed within the logical sub-block of the physical layer. The data link layer is responsible for ensuring that data sent on the link is correct and is responsible to ensure that packets are reliably transmitted on the link. Finally, the transaction layer is responsible for constructing request/completion transactions, transaction layer packet ﬂow control, and messaging. In addition to the serial analyzers, the P6716/P6708 mid-bus probes and pre-release slot interposer probes are available to test and validate all layers of the PCIe 2.0 protocol. The analyzers plug into Tektronix TLA7000 series logic analyzers adding the ability to debug and correlate general purpose signals and other system interconnects including memory and computer processors. PCI Express 2.0 link width and speed negotiation requires debugging the logical sub-block of the physical 40 layer where logic analysis instruments are able to provide detailed data, unlike protocol analysis tools. The TLA7S08 and TLA7S16 analyzers can acquire x1, x4 links or x8 links respectively. Two TLA7S16 Serial Analyzers are used for bi-directional x16 links. PCIe 2.0 links can change width (number of lanes) dynamically. For instance, an eight lane link (x8) could change to 4 lanes (x4) – which requires less power – and return back to x8 when this is needed by the system. The PCIe 2.0 speciﬁcation also allows for the link to dynamically alternate the speed between 2.5 Gb/s to 5 Gb/s, supporting both PCIe 1.0 and 2.0 standards. Additionally, a link can go into idle power states during the short periods of time when it is not being utilized. It is critical to validate that these link operations are performed correctly during the width and speed changes and during transitions to and from power management states. The new Tektronix Serial Analyzers can uniquely validate and debug operation of these link processes. As electronic systems become more complex, integration of parallel and high-speed serial buses in designs is increasingly common. In many cases, it is not possible to debug system level issues by looking only at the PCIe bus. An example would be a case where the PCIe link issues a memory read request to the processor. In turn, the processor issues a memory read request to DDR memory. If the DDR memory reads from the incorrect memory address, the incorrect data will be returned back to the PCIe link and will result in incorrect system behavior. The Tektronix TLA7000 logic analyzer is able to time correlate interactions between PCIe, processors, and memory using a single test platform. The TLA7S08 and TLA7S16 Serial analyzers are complemented by a series of serial acquisition probes. Designers who have the ﬂexibility to incorporate a mid-bus probe will beneﬁt from the superior electrical performance of the P6708 half-width and P6716 full-width midbus probes. Narrower link widths can take advantage of the P6708 footprint that minimizes board real estate. A slot interposer is an alternative probing method for devices that utilize the PCIe slot, such as graphics cards or host channel adapter cards. Pre-release slot interposers are available in x1, x4, x8, and x16 link widths. The Tektronix TLA7000 Series Logic Analyzer, TLA7S16 and TLA7S08 Serial Analyzers, P6716/ P6708 mid-bus probes and the prerelease slot interposer probes are used to test and validate all layers of the PCIe protocol: physical, data link, and transaction layers. Below the logical sub-block of the physical layer is the electrical subblock. Tektronix provides the most capable PCIe 2.0 test solution for the electrical sub-block comprised of industry leading DSA70000 real-time and DSA8200 sampling oscilloscopes, AWG7000 arbitrary waveform generators, and complete test software. www.tektronix.com OCTOBER 2007 | embedded systems design europe | www.embedded.com/europe 040_ESDE.indd 40 11/10/07 11:03:08 http://www.tektronix.com http://www.embedded.com/europe

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Embedded Systems Design Europe - October 2007 Contents Linux Set to Dominate Torvalds Updates Linux Kernel ARM Establishes Smart Card Foundry Program Emerson Buys Motorola's Embedded Comms Group LynuxWroks and TTTech to Cooperate on Avionics MontaVista CEO Looks for Acquisitions in Europe Ready: Multiprocessing Technology Provides Opportunity Automotive to Drive MCU Market New Supporters Join COM Express Group Analyst Weighs TI Versus Xilinx Versus PicoChip Cover Feature: Embedded Systems Security Has Moved to the Forefront Trace Exposes the Toughest Real-Time Bugs Employ a Secure Flavor of Linux Use an MCU's Low-Power Modes in Foreground/Background Systems Transporting Video Over Wireless Networks New Products Advertising Contacts

Embedded Systems Design Europe - October 2007

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