Embedded Systems Design Europe - November 2007 - (Page 16) microcontollers on their I/O pins. Especially complicated are the low pin-count devices, where it’s common to see three or more functions multiplexed onto one pin. It’s easy to see that this multiplexing leads to problems when allocating the MCU’s resources in an embedded system, where the needed peripherals are found multiplexed on the same pins. Here, designers have some options: use higher pin count MCUs where the I/O lines are de-multiplexed; or use additional devices, such as multiplexers and extra glue logic, to get around these I/O line problems. The third option is to implement one of the peripherals in software, such as bit-banging a UART through an I/O pin. With these workarounds, you’ll end up with higher system costs. In addition, if you implement peripheral functions in software, it may result in lesser performance from the MCU, or higher power dissipation due to faster CPU operation. I/O PIN MAPPING IN SOFTWARE There’s another interesting way to address this issue – letting the system designer define the MCU’s pin-out. In other words, simply empower the designers to bring out the required functionality directly to the appropriate pins. Although it sounds revolutionary, the idea is a reality today. Flexible I/O pin mapping is available from a few MCU vendors. The key challenge for MCU vendors in implementing flexible pin mapping is to offer the feature in a manner that avoids potential design violations. These violations could include defining two separate output functions onto the same pin, thus causing output short; or connecting two physical pins to same input function, causing bus contention. Flexible I/O pin mapping is currently available in two flavors. The priority-encoding system shown in Figure 1 defines the MCU’s I/O pin mapping in one approach. Here, the MCU’s peripherals are graded by priority. The highest-priority peripheral takes the initial set of I/O pins, followed by the lower-priority peripherals that take 16 up the remaining I/O pins in the configuration chain. This priority scheme avoids design violations by restricting only one function to each remappable pin, based on priority. The highestpriority function is fixed on one pin, while the lower-priority function can be moved to many pins. Usually, the pin assignment is controlled by some special function registers. Each function can be enabled or disabled with a control bit. If enabled, based on its priority compared with the priority of other functions, the function will show up on one pin. Designers must be careful while assigning pins in software. They need to assign the highest-priority pins first. If you assign lower-priority pins first, then their locations will change as higher-priority functions are enabled. This is a somewhat restricted way of I/O pin mapping. “PICK AND PLACE” I/O PIN MAPPING In the other approach, designers have the freedom to route any I/O to any of the remappable I/O pins. This more flexible approach avoids the priority problems I described and relies on a unique pin-definition interface, based on flexible pin-mapping configuration registers. Designers also get more help from the configuration tool, which alerts them to the listed design violations while enabling true I/O remapping with one-to-many, many-to-one, or many-to-many relationships. Being very flexible, this kind of pin-mapping scheme still needs to be deployed with care, to avoid potential design violations. You can avoid design violations by using a unique pindefinition interface, which helps guard against design violations. For example, to avoid two outputs appearing on one pin, the register configuration is based on defining the function for each pin. As shown in Figure 2, the output on each pin is defined by a coded value in the Special Function Register (SFR). Each value of this bit combination defines one output function. That is, a value of “3” may specify the UART 1 Tx output function, while a value of “7” may specify the SDO line output for SPI. You can only define one value per pin, thereby preventing two outputs from appearing on one pin, while still allowing for the possibility of outputting the same function on multiple pins. The input assignment shown in Figure 3 works the opposite way – the register configuration is based on assigning a pin to each function. For example, an NOVEMBER – DECEMBER 2007 | embedded systems design europe | www.embedded.com/europe 015-016-017-018-019_ESDE.indd 16 6/11/07 13:14:41 http://www.embedded.com/europe
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