Embedded Systems Design Europe - November 2007 - (Page 34) multiprocessing bus interface wrappers associated with the generated hardware as shown in Figure 2. Using such a design flow, it’s practical for a software engineer – one who has experience with embedded systems but not necessarily FPGA design – to specify, generate, and bring-up a complete hardware-accelerated application without having to write HDL for any part of the system. One example of a highly scalable, multi-dimensional, and flexible hybrid processing approach uses hard and/or soft processing cores efficiently attached to scalable coprocessing functions implemented in the soft FPGA logic fabric. Here, a 32-bit processor core is implemented in soft logic. Impulse C tools used to accelerate and generate the soft coprocessing acceleration core to increase the frequency of the FIR filter are shown in Figure 3 and Table 1. The key advantage to this custom accelerated system is computation performance: the C-language FIR filter algorithm coupled tightly to the soft processor via the FSL achieves over 400X acceleration in performance over eration cores, such as a specialized DSP filter, requires either hand coding in HDL or the use of C-to-FPGA tools. For development and prototyping, preconfigured boards can be used to create complete systems-on-an-FPGA. These single-chip systems might in- clude one or more embedded soft processors, processor peripherals, and associated C hardware accelerators. In this use model, the Impulse C compiler serves as a peripheral generator, using platform-specific knowledge and automatically creating all necessary 34 NOVEMBER – DECEMBER 2007 | embedded systems design europe | www.embedded.com/europe 030-031-032-033-034-035_ESDE.ind34 34 12/11/07 11:22:41 http://www.embedded.com/europe
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