Embedded Systems Design - March 2008 - (Page 29)

0308esd.p27to31 2/13/08 7:53 PM Page 29 feature way down to gates and layout. The terms’ grammar, when augmented with details such as instruction formats and sizes of various register ﬁles, buffers, memories, and so on, precisely speciﬁes the state elements. Each rule is then compiled such that the state is read in the beginning of the clock cycle and updated at the end of the clock cycle. This single-cycle implementation methodology automatically enforces the atomicity constraint of each rule. All the enabled rules ﬁre in parallel unless some modify the same state element. In case of such a conﬂict, one of the conﬂicting rules is selected to ﬁre on the basis of some policy. An example of the power that the use of TSR atomicity brings to hardware synthesis is illustrated in Figure 2, in which Euclid’s algorithm for computing the greatest common divisor (GCD) of two numbers is expressed in TSR notation. From this, the Term Rewriting Architectural Compiler generates a Verilog description of the circuit shown in Figure 3. ATOMICITY AND GENERATING HARDWARE/SOFTWARE How do atomic transactions such as those employed in TRSs contrast with other approaches used in software and hardware, such as with C/SystemC, Verilog, and VHDL? Contrasting these approaches with atomicity highlights just how low-level, manually intensive, and fragile these approaches are. In all of these other approaches, coordinating and managing the access to shared resources, which includes both arbitration and control, must be done explicitly and from scratch by the engineer in every instance. This makes these approaches: Euclid’s algorithm for greatest common divisor (GCD) using rewrite rules. Rewrite rules to implement Euclid’s algorithm. R1 GCD a, b → GCD b, a if a > b, b ≠ 0 R2 () () GCD ( a, b ) → GCD ( a, b − a ) if a ≤ b, b ≠ 0 ( Example of rules executing. GCD 6,15 → GCD 6, 9 → GCD 6, 3 → GCD 3, 6 → GCD 3, 3 → GCD 3, 0 Figure 2 ) Apply R2 () Apply R2 ( ) R1 Apply ( ) R2 Apply ( ) R2 Apply () Solution: 3 is the GCD of 6 and 15. • • • Tedious, due to the ad hoc, low-level nature of managing concurrency. Error prone, subject to race condi- tions, interface protocol errors, mistimed data sampling (for hardware), deadlocks, among others. Brittle to changes, requiring the control to be redesigned each time there is a small change in the speciﬁcation or implementation. Another issue with these approaches www.embedded.com | embedded systems design | MARCH 2008 29 http://www.rabbitdevkits.com http://www.embedded.com

Table of Contents Feed for the Digital Edition of Embedded Systems Design - March 2008

Embedded Systems Design - March 2008 Contents #Include Programming Pointers Designing DSP-based Motor Control Using Fuzzy Logic Hardware/Software Verification Enters the Atomic Age Efficient CRC Calculation with Minimal Memory Footprint Programming Your Own Microcontroller Advertising Index Break Points Marketplace

Embedded Systems Design - March 2008

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